Jesús Alastruey Benedé

Profesor Colaborador en el área de Arquitectura y Tecnología de Computadores (ATC) del departamento de Informática e Ingeniería de Sistemas (DIIS), Universidad de Zaragoza (UZ)

Investigador del grupo de Arquitectura de Zaragoza (gaZ)
Anteriormente colaboraba con el grupo de Tecno-Espeleología (GTE)

E-mail: jalastru at unizar dot es
Phone: (+34) 976 76 23 39 / 976 76 19 49 (Secretaría DIIS)
Escuela de Ingeniería y Arquitectura (EINA)
Edificio Ada Byron, C/ María de Luna
50018 Zaragoza, España


CV | Docencia/Teaching | Investigación/Research | Publicaciones/Publications

foto

Docencia/Teaching

La mayor parte de mi labor docente es en el Grado en Ingeniería Informática, concretamente en la especialidad de Ingeniería de Computadores.

Investigación/Research

My present research focuses on memory hierarchy and efficient molecular dynamic simulation

Publicaciones/Publications

Copyright notice: "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to these terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage
[IEEE Xplore] [IEEE Computer] [multimedia (TC)]
A. Ferrerón, D. Suárez-Gracia, J. Alastruey-Benedé, T. Monreal and P. Ibáñez
In IEEE Transactions on Computers, Special Issue on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (IEEE TC 2016)
JCR 2015: Q1.


Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints
[Springer] [pdf]
C.C.K. Mikkelsen, J. Alastruey-Benedé, P. Ibáñez-Marín and P. García-Risueño
Parallel Processing and Applied Mathematics - 11th International Conference (PPAM 2015) , Krakow, Poland, September 6-9, 2015. Revised Selected Papers, Part I. , pp.160-171.
CORE C.

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages
[IEEE Xplore] [pdf] [ppt]
A. Ferrerón, D. Suárez-Gracia, J. Alastruey-Benedé, T. Monreal and V. Viñals-Yúfera
26th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2014) , October 22nd-24th, 2014, Paris, France
CORE B.

Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors
[Springer] [ACM DL] [pdf]
A. Ferrerón-Labari, M. Ortín-Obón, D. Suárez-Gracia, J. Alastruey and V. Viñals-Yúfera
In Proceedings of the 26th International Conference on Architecture of Computing Systems (ARCS 2013) , Prague, february, 2013 pp. 256-267. Springer Berlin / Heidelberg.

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
[IEEE Xplore] [pdf] [ppt]
J. Alastruey, T. Monreal, F. Cazorla, V. Viñals and M. Valero
20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2008) , Campo Grande (Brazil), oct 29-nov 01, 2008, pp. 63
CORE B.

This paper is referenced by three IBM patents:

  1. Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May, Michael D. Snyder, Gary Whisenhunt, James Xenidis.
    Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition.
    US Patent 8615644 B2. December 24, 2013.

  2. Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May, Michael D. Snyder, Gary Whisenhunt, James Xenidis..
    Indicating Disabled Thread To Other Threads When Contending Instructions Complete Execution To Ensure Safe Shared Resource Condition.
    US Patent 9047079 B2. June 2, 2015.

  3. Giles R. Frazier, Michael K. Gschwind, Naresh Nayar.
    Privilege level aware processor hardware resource management facility.
    US Patent 9342337 B2. May 17, 2016.

Microarchitectural Support for Speculative Register Renaming
[IEEE Xplore] [pdf] [ppt]
J. Alastruey, T. Monreal, V. Viñals and M. Valero
International Parallel and Distributed Processing Symposium (IPDPS 2007) , Long Beach (USA), pp. 1-10.
CORE A.

This paper is referenced by two ARM patents:

  1. Luca Scalabrino, Melanie Emanuelle Lucie Teyssier, Cedric Denis Robert Airaud, Guillaume Schon, Weniger.
    Tracking speculative execution of instructions for a register renaming data store.
    US Patent US 9361111 B2. June 7, 2016.

  2. Guillaume Schon, Cedric Denis Robert Airaud, Frederic Jean Denis Arsanto, and Luca Scalabrino.
    Technique For Freeing Renamed Registers.
    US Patent US 9400655 B2. July 26, 2016.

Speculative Early Register Release
[ACM DL] [pdf] [ppt]
J. Alastruey, T. Monreal, V. Viñals and M. Valero
3rd conference on Computing frontiers (CF 2006), Ischia (Italy), pp. 291-302

This paper is referenced by a QUALCOMM patent:

  1. Michael Scott McIlvaine, James Norris Dieffenderfer, Nathan Samuel Nunamaker, Thomas Andrew Sartorius, Rodney Wayne Smith.
    Use of Register Renaming System for Forwarding Intermediate Results Between Constituent Instructions of an Expanded Instruction.
    US Patent US 7669039 B2. February 23, 2010.

Software Demand, Hardware Supply
[IEEE Xplore] [pdf]
J. Alastruey, J.L. Briz, P. Ibañez and V. Viñals
IEEE MICRO, July, 2006. Vol. 26(4), pp. 72-82.
JCR 2006: Q2.

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