Pablo Ibáñez Marín

Profesor Titular en el área de Arquitectura y Tecnología de Computadores (ATC)
Departamento de Informática e Ingeniería de Sistemas (DIIS)
Universidad de Zaragoza (UZ)

Investigador del grupo de Arquitectura de Zaragoza (gaZ)

E-mail: imarin at unizar dot es
Phone: (+34) 976 76 21 07 / 976 76 19 49 (Secretaría DIIS)
Escuela de Ingeniería y Arquitectura (EINA)
Edificio Ada Byron, C/ María de Luna
50018 Zaragoza, España

Perfil Sideral UZ  Google Scholar  ORCID 


| Docencia/Teaching | Investigación/Research |
| Tesis doctorales dirigidas/PhD students | Publicaciones/Publications

foto

Docencia/Teaching

La mayor parte de mi labor docente es en el Grado en Ingeniería Informática, en la especialidad de Ingeniería de Computadores.

Investigación/Research

Mi trabajo actual se desarrolla en las siguientes líneas: políticas de gestión de contenidos en SLLCs (filtrado por reuso, prebúsqueda, …), mejora de la eficiencia de la SLLC en términos de área y consumo energético (alimentación cerca del umbral, uso de nuevas tecnologías para la implementación de SLLC, …) y optimización de aplicaciones (gromacs, FM-index, …)

My present research focuses on the following lines: content management policies in SLLCs (filtering by reuse, prefetching, ...), improvement of the efficiency of the SLLC in terms of area and energy consumption (near threshold computing, use of new technologies for the implementation of SLLC, ...) and application optimization (gromacs, FM-index, ...)

Tesis doctorales dirigidas/PhD students

Jorge Albericio Latorre
Improving the SLLC efficiency by exploiting reuse locality and adjusting prefetch
20-may-2013
Co-advised with José María Llabería Griñó
[pdf] [zaguan] [teseo]

Luis Manuel Ramos Martínez
Alternativas de Diseño en Sistemas de Prebúsqueda Hardware de Datos
22-dic-2012
Co-advised with José Luis Briz Velasco
[pdf] [teseo]

Ana Bosque Arbiol
Filtering directory lookups in CMPs
11-nov-2011
Co-advised with José María Llabería Griñó y Víctor Viñals Yúfera
[pdf] [zaguan] [teseo]

Enrique Torres Moreno
Alternativas de Diseño en Memoria Cache de Primer Nivel Multibanco
30-jun-2005
Co-advised with Víctor Viñals Yúfera
[pdf] [teseo]

Currently co-advising 3 PhD students:
Javier Díaz Maag (gaZ)
Agustín Navarro Torres (gaZ)
Carlos Escuín Blasco (gaZ)

Publicaciones/Publications

Copyright notice: "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to these terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

Peer reviewed/Revisadas por pares

Synchronization Strategies on Many-Core SMT Systems.
[IEEE Xplore] [pdf (accepted manuscript)] [pdf (slides)]
A. Navarro-Torres, M. Carpen-Amarie, J. Alastruey-Benedé and P. Ibáñez-Marín
In Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2021)., 26–29 October 2021, Belo Horizonte, Brasil.

A learning experience toward the understanding of abstraction-level interactions in parallel applications.
[Elsevier open access link]
A. Valero, R. Gran, D. Suárez, E. A. Georgescu, J. Ezpeleta, P. Álvarez, A. Muñoz, L. M. Ramos, P. Ibáñez
Journal of Parallel and Distributed Computing (JPDC). Volume 156, pp. 38-52 , October 2021

Near-optimal replacement policies for shared caches in multicore processors.
[Springer link] [SharedIt] [pdf (preprint manuscript)] [code repository (github)]
Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería
The Journal of Supercomputing (JSC). March 2021

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps.
[IEEE Xplore] [DOI] [pdf (preprint manuscript)] [code repository (github)]
Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó
Accepted for publication in IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB). June 2020

Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor.
[IEEE Xplore] [pdf (preprint manuscript)] [code repository (github)]
José Manuel Herruzo, Sonia González, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, and Óscar Plata
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB 2020). Volume 17, issue 4, pp. 1093-1104 , July-Aug. 2020

Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP.
[PLOS ONE free access]
Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals-Yúfera
PLOS ONE 14(8): e0220135. August 1, 2019.

ReD: A reuse detector for content selection in exclusive shared last-level caches.
[ScienceDirect] [pdf (preprint manuscript)]
Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals
Journal of Parallel and Distributed Computing (JPDC 2019). Volume 125, pp. 106-120 , March 2019

A Fault-Tolerant Last Level Cache for CMPs Operating at Ultra-Low Voltage.
[ScienceDirect] [DOI] [pdf (preprint manuscript)] [slides]
Alexandra Ferrerón, Jesús Alastruey-Benedé, Darío Suárez-Gracia, Teresa Monreal, Pablo Ibáñez and Víctor Viñals
Journal of Parallel and Distributed Computing (JPDC 2019). Volume 125, pp. 31-44 , March 2019

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.
[IEEE Xplore] [pdf] [slides] [DOI]
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique Torres, Pedro Álvarez, Pablo Ibáñez, and Víctor Viñals
In Workshop on Computer Architecture Education (WCAE’19), June 22, 2019, Phoenix, AZ, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/3338698.3338886.

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.
[IEEE Xplore] [pdf] [pdf (poster)]
José Manuel Herruzo, Sonia González, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, and Óscar Plata
In Proceedings of the 2019 Data Compression Conference (DCC 2019), 26–29 March 2019, Snowbird, Utah, USA, pp. 577.

Exact Alignment with FM-index on the Intel Xeon Phi Knights Landing Processor.
[pdf] [slides]
Jose M. Herruzo, Sonia Gonzalez-Navarro, Pablo Ibáñez, Victor Viñals, Jesús Alastruey-Benedé, and Oscar Plata
HPCA 2018 Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), February 24, 2018

ReD: A Policy Based on Reuse Detection for Demanding Block Selection in Last-Level Caches
[CRC-2 pdf] [CRC-2 code]
J. Díaz, P. Ibáñez, T. Monreal, V. Viñals and J. M. Llabería
The 2nd Cache Replacement Championship (CRC-2). Co-located with the 44th ISCA, June 2017
3rd place in the overall ranking of the competition
2nd place in multi-core SPEC with and without prefetch, 1st place in multi-core CloudSuite without prefetch

Reuse Detector: Improving the management of STT-RAM SLLCs
[IEEE Xplore]
R. Rodríguez, J. Díaz, F. Castro, P. Ibáñez, D. Chaver, V. Viñals, J.C. Sáez, M. Prieto, L. Piñuel, T. Monreal, J.M. Llabería
The Computer Journal. (Section B: Computer and Communications Networks and Systems), pp. 1-25, octubre 2017

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage
[IEEE Xplore] [IEEE Computer] [multimedia (TC)] [pdf]
A. Ferrerón, D. Suárez-Gracia, J. Alastruey-Benedé, T. Monreal and P. Ibáñez
In IEEE Transactions on Computers, Special Issue on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (IEEE TC 2016)

Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints
[Springer] [pdf]
C.C.K. Mikkelsen, J. Alastruey-Benedé, P. Ibáñez-Marín and P. García-Risueño
Parallel Processing and Applied Mathematics - 11th International Conference (PPAM 2015) , Krakow, Poland, September 6-9, 2015. Revised Selected Papers, Part I. , pp.160-171.

The Reuse Cache: Downsizing the Shared Last-Level Cache
[IEEE Xplore]
J. Albericio, P. Ibáñez, V. Viñals, and J.M. Llabería
IEEE/ACM International Symposium On Microarchitecture (MICRO-46), Diciembre 7-11, 2013

Exploiting Reuse Locality on Inclusive Shared Last-Level Caches
[ACM Digital Library]
J. Albericio, P. Ibáñez, V. Viñals, and J.M. Llabería
ACM Transactions on Architecture and Code Optimization (TACO). Vol. 9, Issue 4 Enero, 2013

Data prefetching in a cache hierarchy with high bandwidth and capacity
[ACM Digital Library]
L. M. Ramos, J. L. Briz, P. E. Ibáñez, and V. Viñals
ACM SIGARCH Computer Architecture News. Volume 35, Issue 4. Sept., 2013

ABS: A low-cost adaptive controller for prefetching in a banked shared LLC
[ACM Digital Library]
J. Albericio, P. Ibáñez, V. Viñals, and J.M. Llabería
ACM Transactions on Architecture and Code Optimization (TACO). , Vol. 8, Issue 4. Enero, 2012

Efficient handling of lock hand-off in DSM multiprocessors with buffering coherence controllers
[Springer]
B. Sahelices, A. de Dios, P. Ibáñez, V. Viñals-Yúfera, and J.M Llabería
Journal of Computer Science and Technology. Vol. 27, Issue 1, pp.75-91. 2012

A Review of High Performance Computing Foundations for Scientists
[Arxiv]
P. Garcia-Risueño, P. Ibáñez
Journal of Modern Physics C. Volume 23, Issue 7. 4-8 May, 2012

Filtering Directory Lookups in CMPs
[Elsevier]
A. Bosque, V. Viñals, P. Ibáñez, and J.M. Llabería
Microprocessors and Microsystems. Vol. 35, num 8, pp. 695 – 707. Noviembre, 2011

Filtering directory lookups in CMPs with write-through caches
[ACM Digital Library]
A. Bosque, P. Ibáñez, V. Viñals y J. M. Llabería
17th International European Conference on Parallel and Distributed Computing. Proceedings pp. 269-281. Sept., 2011

Multi-level Adaptive Prefetching based on Performance Gradient Tracking
[JILP pdf]
L.M. Ramos, J.L. Briz, P. Ibáñez and V.Viñals
The 1st JILP Data Prefetching Championship (DPC-1). In conjunction with HPCA-15, Febrero 2009
Best Paper Award and third best performance metrics
Journal of Instruction-Level Parallelism. Vol. 13 1-14, 2011

Store Buffer Design for Multibanked Data Caches
[IEEE Xplore]
E. Torres, P. Ibáñez, V. Viñals and J.M. Llabería
IEEE Transactions on Computers. vol. 58, n. 10, pp. 1307-1320. Oct. 2009

A methodology to characterize critical section bottlenecks in DSM multiprocessors
[ACM Digital Library]
B. Sahelices, P. Ibáñez, V. Viñals y J.M. Llabería
15th International Euro-Par Conference. Proceedings pp. 149-161. August 25-28, 2009

Low-cost Adaptive Hardware Prefetching
[ACM Digital Library]
L.M. Ramos, J.L. Briz, P. Ibáñez, and V. Viñals
14th International Euro-Par Conference. Proceedings pp. 327-336. August 26-29, 2008

Software Demand, Hardware Supply
[IEEE Xplore] [pdf]
J. Alastruey, J.L. Briz, P. Ibáñez and V. Viñals
IEEE MICRO. Vol. 26(4), pp. 72-82. July, 2006.

Speeding-up Synchronizations in DSM Multiprocessors
[Springer]
B. Sahelices, A. de Dios, P. Ibáñez, V. Viñals y J.M. Llabería
12th International Euro-Par Conference. Proceedings pp. 475-484. Sept. 2006

Store Buffer Design in First-Level Multibanked Data Caches
[IEEE Xplore]
E. Torres, P. Ibáñez, V. Viñals, and J.M. Llabería
The 32nd Annual International Symposium on Computer Architecture (ISCA). Proceedings, pp. 469-480. 4-8 June, 2005

Contents Management in First-Level Multibanked Data Caches
[Springer]
E.F. Torres, P. Ibáñez, V. Vinals, and J.M.Llaberia
10th International Euro-Par Conference. Proceedings pp. 516–524, Sept. 2004

Counteracting Bank Misprediction in Sliced First-Level Caches
[Springer]
E.F. Torres, P. Ibañez, V. Viñals and J. M. Llabería
10th International Euro-Par Conference. Proceedings pp. 586–596, Aug. 2003

Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware
[IEEE Xplore]
M. J. Garzarán, J. L. Briz, P. Ibáñez and V. Viñals
Ninth Euromicro Workshop on Parallel and Distributed Processing. Proceedings pp. 345-354, 2001

Modelling Load Address Behaviour Trough Recurrences
[IEEE Xplore]
L. Ramos, P. Ibáñez, V. Viñals and J.M. Llabería
2000 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Proceedings pp. 101-108, 2000

Characterization and improvement of Load/Store Cache-based prefetching
[ACM Digital Library]
P. Ibáñez, V. Viñals, J.L. Briz y M.J. Garzarán
International Conference on Supercomputing (ICS'98). Proceedings pp. 369-376, 1998

Performance Assessment of Contents Management in Multilevel On-Chip Caches
[IEEE Xplore]
P. Ibáñez and V. Viñals
22nd Euromicro Conference. Proceedings pp. 431-440, 1996

Warm Time Sampling: Fast and Accurate Cycle-Level Simulation of Cache Memory
[pdf]
L. Jimeno, P. Ibáñez and V. Viñals
22nd Euromicro Conference. Beyond 2000: Hardware/Software Design Strategies: Short Contributions pp. 39-44, 1996

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