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La mayor parte de mi labor docente es en el Grado en Ingeniería Informática, en la especialidad de Ingeniería de Computadores.
En cursos anteriores he impartido
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My present research focuses on the following lines: improvement of the efficiency of the SLLC in terms of area and energy consumption (near threshold computing), and application optimization (efficient molecular dynamics simulations and genomic applications).
Currently collaborating with the Computer Architecture - Operating System Interface (CAOS) group at the Barcelona Supercomputing Center (BSC).
gaZ research lines (spanish)
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Jesús Alastruey-Benedé
Renombre de Registros Especulativo
Sobresaliente Cum Laude. 21-dic-2009
Advised by Teresa Monreal, Víctor Viñals and Mateo Valero
[pdf]
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Tesis doctorales dirigidas/PhD students
Alexandra Ferrerón Labari
Exploiting Natural On-chip Redundancy for Energy Efficient Memory and Computing
Sobresaliente Cum Laude. Mención Doctorado Internacional. 25-nov-2016
Co-advised with Darío Suárez Gracia
[pdf]
[zaguan]
Agustín Navarro Torres
Contributions to High-Performance Memory Hierarchies: Program Characterisation, Resource Control, Transactional Synchronisation, and Hardware Prefetching
Sobresaliente Cum Laude. Mención Doctorado Internacional. 17-abr-2023
Co-advised with Pablo Ibáñez Marín
[pdf]
[slides]
[zaguan]
Currently co-advising 2 PhD students:
Rubén Langarita Benítez (BSC) and
Lorién López Villellas (gaZ)
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Publicaciones/Publications
Copyright notice:
"This material is presented to ensure timely dissemination of scholarly and technical work.
Copyright and all rights therein are retained by authors or by other copyright holders.
All persons copying this information are expected to adhere to these terms and constraints invoked by each author's copyright.
In most cases, these works may not be reposted without the explicit permission of the copyright holder."
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Peer reviewed/Revisadas por pares
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GenArchBench: A Genomics Benchmark Suite for Arm HPC Processors.
[ScienceDirect]
[DOI]
[preprint (pdf)]
Lorién López-Villellas, Rubén Langarita-Benítez, Asaf Badouh, Víctor Soria-Pardos, Quim Aguado-Puig, Guillem López-Paradís, Max Doblas, Javier Setoain, Chulho Kim, Makoto Ono, Adrià Armejach, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó
In Future Generation Computer Systems, volume 157, August 2024, pages 313-329.
JCR 2022: Q1.
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RISC-V for Genome Data Analysis: Opportunities and Challenges.
[IEEE Xplore]
[DOI]
[accepted manuscript (pdf)]
Lorién López-Villellas, Esteve Pineda-Sánchez, Asaf Badouh, Santiago Marco-Sola, Pablo Ibáñez, Jesús Alastruey-Benedé, and Miquel Moretó
proceedings of the XXXVIII Conference on Design of Circuits and Integrated Systems (DCIS 2023), Málaga, Spain, 2023, pp. 1-6.
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Porting and optimizing BWA-MEM2 using the Fujitsu A64FX processor.
[IEEE Xplore]
[DOI]
[accepted manuscript (pdf)]
[code repository]
Rubén Langarita, Adrià Armejach, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB). Vol. 20, no. 5, pp. 3139-3153, 1 Sept.-Oct. 2023.
JCR 2022: Q1.
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Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code.
[ScienceDirect]
[DOI]
[pdf]
[code repository (GitHub)]
Lorién López-Villellas, Carl Christian Kjelgaard Mikkelsen, Juan José Galano-Frutos, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó, Javier Sancho, and Pablo García-Risueño
Computer Physics Communications.
Volume 288, July 2023.
JCR 2022: Q1.
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BALANCER: Bandwidth Allocation and Cache Partitioning for Multicore Processors.
[SpringerLink]
[DOI]
[final article (pdf)]
[code repository (GitHub)]
Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Víctor Viñals-Yúfera
The Journal of Supercomputing.
Volume 79, issue 9, pp. 10252-10276, June 2023.
JCR 2022: Q2.
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Berti: an Accurate Local-Delta Data Prefetcher.
[IEEE Xplore]
[accepted manuscript (pdf)]
[code repository (GitHub)]
[slides]
Agustín Navarro-Torres, Biswabandan Panda, J. Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals-Yúfera, and Alberto Ros
55th ACM/IEEE International Symposium on Microarchitecture (MICRO 2022)
, October 1-5, 2022, Chicago, Illinois, USA, pp. 975-991.
GGS 2 (A).
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Synchronization Strategies on Many-Core SMT Systems.
[IEEE Xplore]
[accepted manuscript (pdf)]
[slides]
Agustín Navarro-Torres, Maria Carpen-Amarie, J. Alastruey-Benedé, and Pablo Ibáñez-Marín
33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2021)
, October 26-29, 2021, Belo Horizonte, Brasil, pp. 54-63.
CORE B.
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Developing an AI IoT application with open software on a RISC-V SoC.
[IEEE Xplore]
[DOI]
[accepted manuscript (pdf)]
Enrique Torres-Sánchez, Jesús Alastruey-Benedé, and Enrique Torres-Moreno
Proceedings of the XXXV
Conference on Design of Circuits and Integrated Systems (DCIS 2020), Segovia, Spain, 2020, pp. 1-6.
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Expanding the Limits of Computer-Assisted Sperm Analysis through the Development of Open Software.
[MDPI]
[DOI]
Jesús Yániz, Carlos Alquézar-Baeta, Jorge Yagüe-Martínez, Jesús Alastruey-Benedé, Inmaculada Palacín, Sergii Boryshpolets, Vitaliy Kholodnyy, Hermes Gadêlha and Rosaura Pérez-Pe
Biology 2020, volume 9, issue 8, article number 207.
Selected as cover story of the issue.
Part of the Special Issue Factors Affecting In Vitro Assessment of Sperm Quality
JCR 2020: Q1.
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Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps.
[IEEE Xplore]
[DOI]
[accepted manuscript (pdf)]
[code repository]
Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB).
Volume: 19, Issue: 1, pp. 355-368, Jan/Feb 2022. Print ISSN: 1545-5963. Online ISSN: 1557-9964.
JCR 2022: Q1.
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Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP.
[PLOS ONE]
[final article (pdf)]
[code repository (GitHub)]
Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Víctor Viñals-Yúfera
PLOS ONE 14(8): e0220135. Volume 14, number 8, pp. 1-24. August 2019.
https://doi.org/10.1371/journal.pone.0220135.
JCR 2019: Q2.
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Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.
[IEEE Xplore]
[pdf]
[slides]
[DOI]
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique Torres, Pedro Álvarez, Pablo Ibáñez, and Víctor Viñals
Proceedings of the ISCA 2019 Workshop on Computer Architecture Education (WCAE’19), June 22, 2019, Phoenix, AZ, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/3338698.3338886.
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Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.
[IEEE Xplore]
[pdf]
[pdf (poster)]
José Manuel Herruzo, Sonia González, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, and Óscar Plata
Proceedings of the 2019 Data Compression Conference (DCC 2019), 26–29 March 2019, Snowbird, Utah, USA, pp. 577.
CORE 2018: A*.
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Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor.
[IEEE Xplore]
[DOI]
[accepted manuscript (pdf)]
[code repository (GitHub)]
José Manuel Herruzo, Sonia González, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, and Óscar Plata
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB).
Volume: 17, Issue: 4, pp. 1093-1104, July/August 2020. Print ISSN: 1545-5963. Online ISSN: 1557-9964.
JCR 2020: Q1.
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A Fault-Tolerant Last Level Cache for CMPs Operating at Ultra-Low Voltage.
[ScienceDirect]
[DOI]
[accepted manuscript (pdf)]
[slides]
Alexandra Ferrerón, Jesús Alastruey-Benedé, Darío Suárez-Gracia, Teresa Monreal, Pablo Ibáñez and Víctor Viñals
Journal of Parallel and Distributed Computing (JPDC). Volume 125, March 2019, pp. 31-44.
JCR 2019: Q2.
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AISC: Approximate Instruction Set Computer.
[IEEE Xplore]
[pdf]
Alexandra Ferrerón, Jesús Alastruey-Benedé, Darío Suárez-Gracia, and Ulya R. Karpuzcu
ASPLOS 2018 Workshop on Approximate Computing Across the Stack (WAX 2018)
, March 24, 2018, Williamsburg, Virginia, USA
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Exact Alignment with FM-index on the Intel Xeon Phi Knights Landing Processor.
[pdf]
[slides]
Jose M. Herruzo, Sonia Gonzalez-Navarro, Pablo Ibañez, Victor Viñals, Jesús Alastruey-Benedé, and Oscar Plata
HPCA 2018 Workshop on Accelerator Architecture in Computational Biology and Bioinformatics Workshop (AACBB 2018)
, February 24, 2018, Viena, Austria
--
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Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage
[IEEE Xplore]
[IEEE Computer]
[DOI]
[pdf]
[multimedia (TC)]
[multimedia (YouTube)]
A. Ferrerón, D. Suárez-Gracia, J. Alastruey-Benedé, T. Monreal and P. Ibáñez
In IEEE Transactions on Computers, Special Issue on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (IEEE TC 2016). Volume 65, issue 3, March 2016, pp. 755-769.
JCR 2016: Q1.
This article is cited by a patent applied for by AMD:
- AMD.
Michael Scott McIlvaine, James Norris Dieffenderfer, Nathan Samuel Nunamaker, Thomas Andrew Sartorius, Rodney Wayne Smith.
Method and Apparatus for Using Compression to Improve Performance of Low Voltage Caches .
US Patent Application 10,884,940 B2. January 5, 2021.
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Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints
[Springer]
[pdf]
C.C.K. Mikkelsen, J. Alastruey-Benedé, P. Ibáñez-Marín and P. García-Risueño
Parallel Processing and Applied Mathematics - 11th International Conference (PPAM 2015)
, Krakow, Poland, September 6-9, 2015. Revised Selected Papers, Part I., pp.160-171.
CORE C.
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Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages
[IEEE Xplore]
[pdf]
[slides]
A. Ferrerón, D. Suárez-Gracia, J. Alastruey-Benedé, T. Monreal and V. Viñals-Yúfera
26th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2014)
, October 22nd-24th, 2014, Paris, France
CORE B.
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Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors
[Springer]
[ACM DL]
[pdf]
A. Ferrerón-Labari, M. Ortín-Obón, D. Suárez-Gracia, J. Alastruey and V. Viñals-Yúfera
In Proceedings of the 26th International Conference on Architecture of Computing Systems (ARCS 2013)
, Prague, february, 2013 pp. 256-267. Springer Berlin / Heidelberg.
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Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
[IEEE Xplore]
[pdf]
[slides]
J. Alastruey, T. Monreal, F. Cazorla, V. Viñals and M. Valero
20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2008)
, Campo Grande (Brazil), oct 29-nov 01, 2008, pp. 63-70.
CORE B.
This paper is referenced by 12 IBM patents
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Microarchitectural Support for Speculative Register Renaming
[IEEE Xplore]
[pdf]
[slides]
J. Alastruey, T. Monreal, V. Viñals and M. Valero
International Parallel and Distributed Processing Symposium (IPDPS 2007)
, Long Beach (USA), pp. 1-10.
GGS 2 (A). CORE A.
This paper is referenced by four patents (IBM, Qualcomm and ARM x2):
- QUALCOMM. Krishna Anil, Wu Weidan, Navada Sandeep Suresh, Choudhary Niket Kumar, Smith Rodney Wayne.
Freeing Physical Registers In A Microprocessor..
Patent Application WO 2015/142435 A1. Sep 24, 2015.
- ARM. Luca Scalabrino, Melanie Emanuelle Lucie Teyssier, Cedric Denis Robert Airaud, Guillaume Schon, Weniger.
Tracking speculative execution of instructions for a register renaming data store.
US Patent US 9361111 B2. June 7, 2016.
- ARM. Guillaume Schon, Cedric Denis Robert Airaud, Frederic Jean Denis Arsanto, and Luca Scalabrino.
Technique For Freeing Renamed Registers.
US Patent US 9400655 B2. July 26, 2016.
- IBM. Gschwind Michael Karl and Salapura Valentina.
Tracking Operand Liveness Information In A Computer System And Performing Function Based On The Liveness Information.
US Patent 10078515 B2. September 18, 2018.
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Speculative Early Register Release
[ACM DL]
[pdf]
[slides]
J. Alastruey, T. Monreal, V. Viñals and M. Valero
3rd conference on Computing frontiers (CF 2006), Ischia (Italy), pp. 291-302.
GGS 3 (B-).
This paper is referenced by a QUALCOMM patent:
- QUALCOMM.
Michael Scott McIlvaine, James Norris Dieffenderfer, Nathan Samuel Nunamaker, Thomas Andrew Sartorius, Rodney Wayne Smith.
Use of Register Renaming System for Forwarding Intermediate Results Between Constituent Instructions of an Expanded Instruction .
US Patent US 7669039 B2. February 23, 2010.
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Software Demand, Hardware Supply
[IEEE Xplore]
[pdf]
J. Alastruey, J.L. Briz, P. Ibañez and V. Viñals
IEEE MICRO, July, 2006. Vol. 26(4), pp. 72-82.
JCR 2006: Q2.
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Accurate and efficient constrained molecular dynamics of polymers through Newton's method and special purpose code.
[biorXiv]
[pdf]
Lorién López-Villellas, Carl Christian Kjelgaard Mikkelsen, Juan José Galano-Frutos, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó, Javier Sancho, and Pablo García-Risueño
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AISC: Approximate Instruction Set Computer.
[arXiv]
[pdf]
Alexandra Ferrerón, Jesús Alastruey-Benedé, Darío Suárez-Gracia, and Ulya R. Karpuzcu
Long version of
ASPLOS 2018 Workshop on Approximate Computing Across the Stack (WAX 2018) paper
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Mejora del Aprendizaje Mediante Cuestionarios en Línea.
[pdf]
Natalia Ayuso-Escuer, Jesús Alastruey-Benedé
Capítulo del libro "Nuevas técnicas docentes".
Ediciones Pirámide (Grupo Anaya). ISBN 978-84-368-4261-6, Depósito legal: M-37176-2019
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Genalogía Académica/Academic Genealogy
- Antonio Alabau Muñoz, Ph.D. 1972, Universidad Paul Sabatier de Toulouse (Contribution à la conception d'organes numériques de traitement d'information)
- Mateo Valero Cortés, Ph.D. 1980, Universidad Politécnica de Cataluña
- Jesús José Labarta Mancho, Ph.D. 1983, Universidad Politécnica de Cataluña
- Clemente Rodríguez Lafuente, Ph.D. 1986, Universidad Politécnica de Cataluña
- Víctor Viñals Yúfera, Ph.D. 1987, Universidad Politécnica de Cataluña
- Teresa Monreal Arnal, Ph.D. 2003, Universidad de Zaragoza
- Jesús Alastruey Benedé, Ph.D. 2009, Universidad de Zaragoza
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