Publicaciones

Filtro:

R. Gran, J. Segarra, A. Pedro-Zapater, L.C. Aparicio, V. Viñals and C. Rodríguez (2015), "A predictable hardware to exploit temporal reuse in real-time and embedded systems", Journal of Systems Architecture., May, 2015. Vol. 61(5-6), pp. 227-238. Elsevier.
Abstract: In this paper we propose a new hardware data cache (FAFB, fully-associative FIFO tagged buffers) to complement the data cache in processors. It provides predictability when exploiting temporal reuse in array data structures, i.e. it allows an accurate WCET analysis, which is required in real-time systems. With our hardware proposal, compiler transformations that exploit such reuse (essentially tiling) can be safely applied. Moreover, our proposal has other features of particular interest to embedded systems, where a set of well-tuned applications run in a hardware platform which may be constrained in size, complexity and energy consumption. In order to test the most uncommon features of the FAFBs (predictability and effectiveness with a small size), we perform a worst-case analysis on several kernel algorithms for embedded and real-time computing, showing the interaction between tiling and our hardware architecture. Our results show that the number of data cache misses is reduced between 1.3 and 19 times on such algorithms.
BibTeX:
@article{Gran15predictable,
  author = {Rubén Gran and Juan Segarra and Alba Pedro-Zapater and Luis C. Aparicio and Víctor Viñals and Clemente Rodríguez},
  title = {A predictable hardware to exploit temporal reuse in real-time and embedded systems},
  journal = {Journal of Systems Architecture},
  publisher = {Elsevier},
  year = {2015},
  volume = {61},
  number = {5-6},
  pages = {227--238},
  doi = {10.1016/j.sysarc.2015.05.001}
}
J. Segarra, C. Rodríguez, R. Gran, L.C. Aparicio and V. Viñals (2015), "ACDC: Small, Predictable and High-Performance Data Cache", ACM Trans. Embed. Comput. Syst.. New York, NY, USA, February, 2015. Vol. 14(2), pp. 38:1-38:26. ACM.
Abstract: In multitasking real-time systems, the worst-case execution time (WCET) of each task and also the effects of interferences between tasks in the worst-case scenario need to be calculated. This is especially complex in the presence of data caches. In this article, we propose a small instruction-driven data cache (256 bytes) that effectively exploits locality. It works by preselecting a subset of memory instructions that will have data cache replacement permission. Selection of such instructions is based on data reuse theory. Since each selected memory instruction replaces its own data cache line, it prevents pollution and performance in tasks becomes independent of the size of the associated data structures. We have modeled several memory configurations using the Lock-MS WCET analysis method. Our results show that, on average, our data cache effectively services 88% of program data of the tested benchmarks. Such results double the worst-case performance of our tested multitasking experiments. In addition, in the worst case, they reach between 75% and 89% of the ideal case of always hitting in instruction and data caches. As well, we show that using partitioning on our proposed hardware only provides marginal benefits in worst-case performance, so using partitioning is discouraged. Finally, we study the viability of our proposal in the MiBench application suite by characterizing its data reuse, achieving hit ratios beyond 90% in most programs.
BibTeX:
@article{Segarra15ACDC,
  author = {Segarra, Juan and Rodríguez, Clemente and Gran, Rubén and Aparicio, Luis C. and Viñals, Víctor},
  title = {ACDC: Small, Predictable and High-Performance Data Cache},
  journal = {ACM Trans. Embed. Comput. Syst.},
  publisher = {ACM},
  year = {2015},
  volume = {14},
  number = {2},
  pages = {38:1--38:26},
  doi = {10.1145/2677093}
}
J. Segarra, C. Rodríguez, R. Gran, L.C. Aparicio and V. Viñals (2014), "Una cache de datos pequeña y efectiva para sistemas de tiempo real multitarea", In XVII Jornadas de Tiempo Real. Zaragoza, January, 2014.
BibTeX:
@inproceedings{Segarra14cache,
  author = {J. Segarra and C. Rodríguez and R. Gran and L. C. Aparicio and V. Viñals},
  title = {Una cache de datos pequeña y efectiva para sistemas de tiempo real multitarea},
  booktitle = {XVII Jornadas de Tiempo Real},
  year = {2014}
}
R. Gran, J. Segarra, C. Rodriguez, L.C. Aparicio and V. Viñals (2013), "Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems", Journal of Systems Architecture., October, 2013. Vol. 59(9), pp. 667-678. Elsevier.
Abstract: In real-time systems, time is usually so critical that other parameters such as energy consumption are often not even considered. However, optimizing the worst energy consumption case can be a key factor in systems with severe power-supply limitations. In this paper we study several memory architectures using combined time and energy optimization models for real-time multitasking systems. Each task is modeled using Lock-MS, a method to optimize the WCET of a task, with an added set of constraints to model in the same way the WCEC (worst case energy consumption). Our tested hardware components focus on instruction fetching, including a lockable cache, a line buffer and a sequential prefetch buffer. We test a variety of instruction fetch alternatives optimizing time and energy consumption. Our results show that the accuracy of the estimation of the number of context switches in the worst case may affect very much the resulting WCEC (up to 8 times in our experiments) and that optimizing the WCEC may provide similar execution times than optimizing the WCET, with up to 5 times less energy consumption Additionally optimization functions combining WCET and WCEC with different weights show very interesting WCET-WCEC trade-offs. This confirms that methodologies testing such optimizations at design time could be very helpful to provide a precise system set-up.
BibTeX:
@article{Gran13Optimizing,
  author = {R. Gran and J. Segarra and C. Rodriguez and L. C. Aparicio and V. Viñals},
  title = {Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems},
  journal = {Journal of Systems Architecture},
  publisher = {Elsevier},
  year = {2013},
  volume = {59},
  number = {9},
  pages = {667--678},
  doi = {10.1016/j.sysarc.2013.07.012}
}
J. Segarra, C. Rodríguez, R. Gran, L.C. Aparicio and V. Viñals (2012), "A small and effective data cache for real-time multitasking systems", In IEEE Real-Time and Embedded Technology and Applications Symposium. Beijing, China, April, 2012. , pp. 45-54. IEEE Computer Society Press.
Abstract: In multitasking real-time systems, the WCET of each task and also the effects of interferences between tasks in the worst-case scenario need to be calculated. This is especially complex with data caches. In this paper, we propose a small instruction-driven data cache (256 bytes) that effectively exploits locality. It works by preselecting a subset of memory instructions that will have data cache replacement permission. Selection of such instructions is based on data reuse theory. Since each selected memory instruction replaces its own data cache line, it prevents pollution and performance in tasks becomes independent of the size of the associated data structures. We have modeled several memory configurations using the Lock-MS WCET analysis method. Our results show that, on average, our data cache effectively services 88% of program data. Such results translate into doubling the performance of the tested real-time multitasking experiments, which (increasing from 75 to 89%) approaches the ideal case of always hitting in instruction and data caches. Additionally, we show that using partitioning on our proposed hardware only provides marginal benefits.
BibTeX:
@inproceedings{Segarra12Small,
  author = {J. Segarra and C. Rodríguez and R. Gran and L. C. Aparicio and V. Viñals},
  title = {A small and effective data cache for real-time multitasking systems},
  booktitle = {IEEE Real-Time and Embedded Technology and Applications Symposium},
  publisher = {IEEE Computer Society Press},
  year = {2012},
  pages = {45--54},
  doi = {10.1109/RTAS.2012.11}
}
L.C. Aparicio, J. Segarra, C. Rodríguez and V. Viñals (2011), "Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems", Journal of Systems Architecture., August, 2011. Vol. 57(7), pp. 695-706. Elsevier.
Abstract: In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. The difficulty in these cache-locking methods lies in obtaining a good selection of the memory lines to be locked into cache. In this paper, we propose an ILP-based method to select the best lines to be loaded and locked into the instruction cache at each context switch (dynamic locking), taking into account both intra-task and inter-task interferences, and we compare it with static locking. Our results show that, without cache, the spatial locality captured by a line buffer doubles the performance of the processor. When adding a lockable instruction cache, dynamic locking systems are schedulable with a cache size between 12.5% and 50% of the cache size required by static locking. Additionally, the computation time of our analysis method is not dependent on the number of possible paths in the task. This allows us to analyze large codes in a relatively short time (100 KB with 1065 paths in less than 3 min).
BibTeX:
@article{Aparicio10Improving,
  author = {L. C. Aparicio and J. Segarra and C. Rodríguez and V. Viñals},
  title = {Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems},
  journal = {Journal of Systems Architecture},
  publisher = {Elsevier},
  year = {2011},
  volume = {57},
  number = {7},
  pages = {695--706},
  doi = {10.1016/j.sysarc.2010.08.008}
}
L.C. Aparicio, J. Segarra, C. Rodríguez and V. Viñals (2010), "Combining prefetch with instruction cache locking in multitasking real-time systems", In Proceedings of the IEEE Int. Conf. on Embedded and Real-Time Computing Systems and Applications. Macau SAR, China, August, 2010. , pp. 319-328. IEEE Computer Society Press.
Abstract: In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is complex with variable latency hardware usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. Lock-MS is an ILP based method to obtain the best selection of memory lines to be locked in a dynamic locking instruction cache. In this paper we first propose a simple memory architecture implementing the next-line tagged prefetch, specially designed for hard real-time systems. Then, we extend Lock-MS to add support for hardware instruction prefetch. Our results show that the WCET of a system with prefetch and an instruction cache with size 5% of the total code size is better than that of a system having no prefetch and cache size 80% of the code. We also evaluate the effects of the prefetch penalty on the resulting WCET, showing that a system without prefetch penalties has a worst-case performance 95% of the ideal case. This highlights the importance of a good prefetch design. Finally, the computation time of our analysis method is relatively short, analyzing tasks of 96~KB with $10^65$~paths in less than 3~minutes.
BibTeX:
@inproceedings{Aparicio10Combining,
  author = {L. C. Aparicio and J. Segarra and C. Rodríguez and V. Viñals},
  title = {Combining prefetch with instruction cache locking in multitasking real-time systems},
  booktitle = {Proceedings of the IEEE Int. Conf. on Embedded and Real-Time Computing Systems and Applications},
  publisher = {IEEE Computer Society Press},
  year = {2010},
  pages = {319--328},
  doi = {10.1109/RTCSA.2010.8}
}
L. Aparicio, J. Segarra, C. Rodríguez, J. Villarroel and V. Viñals (2008), "Avoiding the WCET Overestimation on LRU Instruction Cache", In Embedded and Real-Time Computing Systems and Applications, 2008. RTCSA '08. 14th IEEE International Conference on., August, 2008. , pp. 393-398.
Abstract: The WCET computation is one of the main challenges in hard real-time systems, since all further analysis is based on this value. The complexity of this problem leads existing analysis methods to compute WCET bounds instead of the exact WCET. In this work we propose a technique to compute the exact instruction fetch contribution to the WCET (IFC-WCET) in presence of a LRU instruction cache. We prove that an exact computation does not need to analyze the full exponential number of possible execution paths, but only a bounded subset of them. In the benchmark codes we have studied, the IFC-WCET is up to 62% lower than a bound computed with a widely used approach, and the difference between the number of possible execution paths and the ones relevant for the analysis is extremely large.
BibTeX:
@inproceedings{Aparicio08Avoiding,
  author = {Aparicio, L.C. and Segarra, J. and Rodríguez, C. and Villarroel, J.L. and Viñals, V.},
  title = {Avoiding the WCET Overestimation on LRU Instruction Cache},
  booktitle = {Embedded and Real-Time Computing Systems and Applications, 2008. RTCSA '08. 14th IEEE International Conference on},
  year = {2008},
  pages = {393--398},
  doi = {10.1109/RTCSA.2008.10}
}
L.C. Aparicio, J. Segarra, V. Viñals, C.Rodríguez and J.L. Villarroel (2008), "Tightening the WCET Bound through Path Pruning", In Actas de las XIX Jornadas de Paralelismo. Castellón, Spain, September, 2008. , pp. 565-570.
BibTeX:
@inproceedings{Aparicio08Tightening,
  author = {L. C. Aparicio and J. Segarra and V. Viñals and C.Rodríguez and J. L. Villarroel},
  title = {Tightening the WCET Bound through Path Pruning},
  booktitle = {Actas de las XIX Jornadas de Paralelismo},
  year = {2008},
  pages = {565--570}
}
V. Cholvi and J. Segarra (2008), "Analysis and placement of storage capacity in large distributed video servers", Computer Communications. Vol. 31(15), pp. 3604-3612. Elsevier.
Abstract: In this paper, we study how to distribute storage capacity along a hierarchical system with cache-servers located at each node. This system is intended to deliver stored video streams in a video-on-demand way, ensuring that, once started, a transmission will be completed without any delay or quality loss. We use off-line smoothing for videos, dividing them into CBR video parts. Also, our request rates are distributed following a 24 h audience curve. In this system, when a request is received, the server reserves the required bandwidth at the required time slots, trying to serve the video as soon as possible. We perform a detailed analysis by means of simulations of the start-up time delay for some storage distributions. It shows that an adequate storage distribution can increase performance about 25% with respect to a uniform distribution and about 47% with respect to one in which all the storage is attached to the gateway routers that connect the final users. We also analyze bandwidth usage, comparing the behavior of these storage distributions. Finally, we present a method which allows dynamic and transparent video reallocations when their popularity changes.
BibTeX:
@article{Segarra08Analysis,
  author = {Vicent Cholvi and Juan Segarra},
  title = {Analysis and placement of storage capacity in large distributed video servers},
  journal = {Computer Communications},
  publisher = {Elsevier},
  year = {2008},
  volume = {31},
  number = {15},
  pages = {3604--3612},
  doi = {10.1016/j.comcom.2008.06.012}
}
L.C. Aparicio, J. Segarra, J.L. Villarroel, V. Viñals and C. Rodríguez (2007), "Instruction Fetch Contribution to Exact WCET in Systems with Cache", In Actas de las XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007). Zaragoza, Spain, September, 2007. , pp. 809-816.
BibTeX:
@inproceedings{Aparicio07Instruction,
  author = {L. C. Aparicio and J. Segarra and J. L. Villarroel and V. Viñals and C. Rodríguez},
  title = {Instruction Fetch Contribution to Exact WCET in Systems with Cache},
  booktitle = {Actas de las XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007)},
  year = {2007},
  pages = {809--816}
}
(2007), "XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007).", September, 2007.
BibTeX:
@proceedings{Ibanez07jpar,,
  editor = {Pablo Ibáñez and Enrique Torres and Juan Segarra and Jesús Alastruey and Luis Manuel Ramos},
  title = {XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007).},
  year = {2007}
}
F. Sanmartín, E. Torres, J. Segarra and U. Arronategui (2007), "El uso de encaminadores domésticos en el entorno docente", In Actas de las XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007). Zaragoza, Spain, September, 2007. , pp. 939-946.
BibTeX:
@inproceedings{Sanmartin07Encaminadores,
  author = {Francisco Sanmartín and Enrique Torres and Juan Segarra and Unai Arronategui},
  title = {El uso de encaminadores domésticos en el entorno docente},
  booktitle = {Actas de las XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007)},
  year = {2007},
  pages = {939--946}
}
J. Segarra and V. Cholvi (2007), "Convergence of periodic broadcasting and video-on-demand", Computer Communications. Vol. 30(5), pp. 1136-1141. Elsevier.
Abstract: Research on video-on-demand transmissions is essentially divided into periodic broadcasting methods and on-demand methods. Periodic broadcasting is aimed to schedule transmissions off-line, so that an optimized time schedule is achieved. On the other hand video-on-demand has to deal with constraints at requesting times. Thus, studies on these areas have been quite isolated. Obviously, in periodic broadcasting all parameters are known in advance, so timetables can be accurately adjusted and it is assumed transmissions can be arranged to use less bandwidth than video-on-demand. In this paper, we analyze the convergence of both paradigms, showing that the claims that argue that VoD schemes use more bandwidth than PB ones are not necessarily true. We state this argument by proving how to convert any periodic broadcasting method into an on-demand one, which will use equal or less bandwidth. Moreover, we show that this converted on-demand method can also offer shorter serving times.
BibTeX:
@article{Segarra07Convergence,
  author = {Juan Segarra and Vicent Cholvi},
  title = {Convergence of periodic broadcasting and video-on-demand},
  journal = {Computer Communications},
  publisher = {Elsevier},
  year = {2007},
  volume = {30},
  number = {5},
  pages = {1136--1141},
  note = {Advances in Computer Communications Networks},
  doi = {10.1016/j.comcom.2006.12.007}
}
L.C. Aparicio, J. Segarra, J.L. Villarroel and V. Viñals (2006), "Cálculo del WCET en Presencia de Memorias Cache", In Actas de las IX Jornadas de Tiempo Real. Valladolid, Spain, February, 2006. , pp. 4.
BibTeX:
@inproceedings{Aparicio06Calculo,
  author = {L. C. Aparicio and J. Segarra and J. L. Villarroel and V. Viñals},
  title = {Cálculo del WCET en Presencia de Memorias Cache},
  booktitle = {Actas de las IX Jornadas de Tiempo Real},
  year = {2006},
  pages = {4}
}
L.C. Aparicio, J. Segarra, J.L. Villarroel and V. Viñals (2006), "Execution Path Pruning for WCET Analysis", In Actas de las XVII Jornadas de Paralelismo. Albacete, Spain, September, 2006. , pp. 615-622.
BibTeX:
@inproceedings{Aparicio06Execution,
  author = {L. C. Aparicio and J. Segarra and J. L. Villarroel and V. Viñals},
  title = {Execution Path Pruning for WCET Analysis},
  booktitle = {Actas de las XVII Jornadas de Paralelismo},
  year = {2006},
  pages = {615--622}
}
L.C. Aparicio, J. Segarra, J.L. Villarroel and V. Viñals (2006), "WCET Computation in Presence of Caches", In Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) Poster Abstracts. L'Aquila, Italy, July, 2006. , pp. 205-208.
BibTeX:
@inproceedings{Aparicio06WCET,
  author = {L. C. Aparicio and J. Segarra and J. L. Villarroel and V. Viñals},
  title = {WCET Computation in Presence of Caches},
  booktitle = {Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) Poster Abstracts},
  year = {2006},
  pages = {205--208}
}
L.C. Aparicio, J. Segarra, J.L. Villarroel and V. Viñals (2005), "Cálculo del Peor Caso en la Cache de Datos", In Actas de las XVI Jornadas de Paralelismo. Granada, Spain, September, 2005. , pp. 329-336.
BibTeX:
@inproceedings{Aparicio05Calculo,
  author = {L. C. Aparicio and J. Segarra and J. L. Villarroel and V. Viñals},
  title = {Cálculo del Peor Caso en la Cache de Datos},
  booktitle = {Actas de las XVI Jornadas de Paralelismo},
  year = {2005},
  pages = {329--336}
}
L.C. Aparicio, J. Segarra, J.L. Villarroel and V. Viñals (2005), "Memorias Cache en Sistemas de Tiempo Real", In Actas de las VIII Jornadas de Tiempo Real. Bilbao, Spain, February, 2005. , pp. 251-258.
BibTeX:
@inproceedings{Aparicio05Memorias,
  author = {L. C. Aparicio and J. Segarra and J. L. Villarroel and V. Viñals},
  title = {Memorias Cache en Sistemas de Tiempo Real},
  booktitle = {Actas de las VIII Jornadas de Tiempo Real},
  year = {2005},
  pages = {251--258}
}
J. Segarra and V. Cholvi (2004), "On-line advancement of transmission plans in video-on-demand", In Distributed Computing Systems Workshops, 2004. Proceedings. 24th International Conference on., March, 2004. , pp. 158-163.
Abstract: We detail an algorithm for the transmission of video-on-demand, which allows transmissions to be advanced dynamically when there is enough bandwidth. The effect is a transmission speed-up and consequently the freeing of bandwidth reservations in the future. This freed bandwidth can therefore be used by other transmissions. We evaluate two basic criteria for producing these advancements, and also detail how this scheme can be combined with other existing on-demand transmission methods. In our experiments we have combined it with an implementation of patching. We compare the performance of our algorithm with this model, and also with a system without merging taken as a reference. We demonstrate that, during the high audience period, delays resulting from our approach are about 44 % lower than without advancements, and we also state the importance of the criteria used for these advancements.
BibTeX:
@inproceedings{Segarra04online,
  author = {Segarra, J. and Cholvi, V.},
  title = {On-line advancement of transmission plans in video-on-demand},
  booktitle = {Distributed Computing Systems Workshops, 2004. Proceedings. 24th International Conference on},
  year = {2004},
  pages = {158--163},
  doi = {10.1109/ICDCSW.2004.1284025}
}
J. Segarra (2003), "Advancing Transmissions with Stream Merging for Video-on-Demand", In Actas de las XI Jornadas de Concurrencia. Benicassim (España), June, 2003. , pp. 321-331.
BibTeX:
@inproceedings{Segarr03Advancing,
  author = {Juan Segarra},
  title = {Advancing Transmissions with Stream Merging for Video-on-Demand},
  booktitle = {Actas de las XI Jornadas de Concurrencia},
  year = {2003},
  pages = {321--331}
}
J. Segarra (2003), "Efficient Data Transmission and Distribution of Resources in Video-on-Demand Systems". Thesis at: Universitat Jaume I., July, 2003.
BibTeX:
@phdthesis{Segarr03Efficient,
  author = {Juan Segarra},
  title = {Efficient Data Transmission and Distribution of Resources in Video-on-Demand Systems},
  school = {Universitat Jaume I},
  year = {2003}
}
J. Segarra and V. Cholvi (2003), "Simulations on Batching in Video-on-Demand Transmissions", In Computational Science ? ICCS 2003. Vol. 2660, pp. 453-462. Springer Berlin Heidelberg.
Abstract: One of the methods for taking advantage of multicast services is the use of batching. With this method, several request of the same video are grouped and transmitted together, using only the bandwidth required for one transmission. This method is commonly used in transmission of streamed data. In this paper we analyze the system performance with explicit constant batching, and demonstrate that a system without explicit batching performs better in terms of delays. We also propose a dynamic batching policy which improves the system performance both in mean and in maximum serving times.
BibTeX:
@incollection{Segarra03Simulations,
  author = {Segarra, Juan and Cholvi, Vicent},
  editor = {Sloot, PeterM.A. and Abramson, David and Bogdanov, AlexanderV. and Gorbachev, YuriyE. and Dongarra, JackJ. and Zomaya, AlbertY.},
  title = {Simulations on Batching in Video-on-Demand Transmissions},
  booktitle = {Computational Science ? ICCS 2003},
  publisher = {Springer Berlin Heidelberg},
  year = {2003},
  volume = {2660},
  pages = {453--462},
  doi = {10.1007/3-540-44864-0_47}
}
J. Segarra and V. Cholvi (2002), "On the Convenience of Using Explicit Batching in Video-on-Demand", In Actas de las X Jornadas de Concurrencia. Jaca (España), June, 2002. , pp. 117-132.
BibTeX:
@inproceedings{Segarra02Convenience,
  author = {Juan Segarra and Vicente Cholvi},
  title = {On the Convenience of Using Explicit Batching in Video-on-Demand},
  booktitle = {Actas de las X Jornadas de Concurrencia},
  year = {2002},
  pages = {117--132}
}
J. Segarra and V. Cholvi (2002), "Placement of storage capacity in distributed video servers", In Communications, 2002. ICC 2002. IEEE International Conference on., April, 2002. Vol. 4, pp. 2537-2541 vol.4.
Abstract: We study how to distribute storage capacity along a hierarchical system with cache-servers located at each node. This system is intended to deliver stored video streams in a video-on-demand way, ensuring that, once started, a transmission is completed without any delay or loss of quality. We perform a detailed analysis of the start-up time delay for some storage distributions, showing that an "intelligent" storage distribution can increase performance from 22% to 29% with respect to a uniform one and from 44% to 78% with respect to one in which all the storage is attached to the gateway router that connects the final users. We also analyze bandwidth usage, comparing the behavior of these storage distributions.
BibTeX:
@inproceedings{Segarra02Placement,
  author = {Segarra, J. and Cholvi, V.},
  title = {Placement of storage capacity in distributed video servers},
  booktitle = {Communications, 2002. ICC 2002. IEEE International Conference on},
  year = {2002},
  volume = {4},
  pages = {2537--2541 vol.4},
  doi = {10.1109/ICC.2002.997300}
}
J. Segarra and V. Cholvi (2001), "Distribution of Video-on-Demand in Residential Networks", In Interactive Distributed Multimedia Systems. Vol. 2158, pp. 50-61. Springer Berlin Heidelberg.
Abstract: In this paper, we study how to distribute cache sizes into a tree structured server for transmitting video streams through videoon-demand (VoD) way. We use off-line smoothing for videos and our request rates are distributed according to a 24 hour audience curve. For this purpose we have designed a slotted-time bandwidth reservation algorithm, which has been used to simulate our experiments. Our system tests the quality of service (QoS) in terms of starting delay, and once a transmission has started, the system guarantees that it will be transmitted without any delay or quality loss. We tested it for a wide range of users (from 800 to 240 000) and also for a different number of available videos. We demonstrate that a tree structured system with uniform cache sizes performs better than the equivalent system with a proxy-like configuration. We also study delay distribution and bandwidth usage in our system on a representative case.
BibTeX:
@incollection{Segarra01Distribution,
  author = {Segarra, Juan and Cholvi, Vicent},
  editor = {Shepherd, Doug and Finney, Joe and Mathy, Laurent and Race, Nicholas},
  title = {Distribution of Video-on-Demand in Residential Networks},
  booktitle = {Interactive Distributed Multimedia Systems},
  publisher = {Springer Berlin Heidelberg},
  year = {2001},
  volume = {2158},
  pages = {50--61},
  doi = {10.1007/3-540-44763-6_7}
}
J. Segarra and V. Cholvi (2001), "Placement of Video Streams in Residential Networks", In Actas de las IX Jornadas de Concurrencia. Sitges (España), June, 2001. , pp. 353-362.
BibTeX:
@inproceedings{Segarra01Placement,
  author = {Juan Segarra and Vicente Cholvi},
  title = {Placement of Video Streams in Residential Networks},
  booktitle = {Actas de las IX Jornadas de Concurrencia},
  year = {2001},
  pages = {353--362}
}

Listado basado en JabRef.

Contacto

Juan Segarra Flor
Profesor Contratado Doctor
Ingeniero en Informática
Doctor por la Universitat Jaume I

Correo electrónico: jsegarra@unizar.es
Web: webdiis.unizar.es/~jsegarra/
Teléfono: (+34) 976 76 2109

Despacho D0.16
Edificio Ada Byron, María de Luna, 1
Departamento de Informática e Ingeniería de Sistemas (DIIS)
Escuela de Ingeniería y Arquitectura
Universidad de Zaragoza
50018 Zaragoza, España

Más información

Miembro del grupo de Arquitectura de Computadores de la Universidad de Zaragoza (gaZ)

Miembro del Instituto Universitario de Investigación en Ingeniería de Aragón (I3A)

Miembro de la European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)

ID ORCID: orcid.org/0000-0003-1550-735X