publications

List of never up-to-date publications.

oficial publication lists

Look me up in DBLP or ORCID.

list of publications

2026

  1. vs2026.jpg
    Floating-point atomic memory operations
    Víctor Soria-Pardos, Adrià Armejach, Darío Suárez, and 1 more author
    Microprocessors and Microsystems, 2026
    DOI
  2. samu2026.gif
    BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores
    Samuel Pérez Pedrajas, Javier Resano, and Darı́o Suárez Gracia
    IEEE Trans. Circuits Syst. Artif. Intell., 2026
    DOI

2025

  1. vs_flama2026.png
    FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems
    Vı́ctor Soria Pardos, Adrià Armejach, Darı́o Suárez Gracia, and 3 more authors
    In 28th Euromicro Conference on Digital System Design, DSD 2025, Salerno, Italy, September 10-12, 2025, 2025
    DOI
  2. juan_tuples.gif
    Tuple Spaces for Workflow Scheduling and Core-Level Malleability in Hpc
    Juan Asensio Ayesa, Darı́o Suárez Gracia, and Lluı́s Castrillo-Acuña
    In 32nd IEEE International Conference on High Performance Computing, Data, and Analytics, HiPC 2025, Hyderabad, India, December 17-20, 2025, 2025
    DOI
  3. micro25-14-fig2.jpg
    Delegato: Locality-Aware Atomic Memory Operations on Chiplets
    Vı́ctor Soria Pardos, Adrià Armejach, Tiago Mück, and 3 more authors
    In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, MICRO 2025, Seoul, Republic of Korea, October 18-22, 2025, 2025
    DOI

2024

  1. spectralwaste2024.png
    SpectralWaste Dataset: Multimodal Data for Waste Sorting Automation
    Sara Casao, Fernando Peña, Alberto Sabater, and 4 more authors
    In IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2024, Abu Dhabi, United Arab Emirates, October 14-18, 2024, 2024
    DOI

2023

  1. dynamo.png
    DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations
    Vı́ctor Soria Pardos, Adrià Armejach, Tiago Mück, and 4 more authors
    In Proceedings of the 50th Annual International Symposium on Computer Architecture, ISCA 2023, Orlando, FL, USA, June 17-21, 2023, 2023
    DOI

2022

  1. A cross-platform OpenVX library for FPGA accelerators
    Maria Angélica Dávila-Guzmán, Lester Kalms, Ruben Gran Tejero, and 3 more authors
    J. Syst. Archit., 2022
    DOI
  2. Lightweight asynchronous scheduling in heterogeneous reconfigurable systems
    Andrés Rodrı́guez, Angeles G. Navarro, Kris Nikov, and 4 more authors
    J. Syst. Archit., 2022
    DOI
  3. peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter
    Darı́o Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, and 2 more authors
    In 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022, Pamplona, Spain, November 16-18, 2022, 2022
    DOI
  4. Efficient Semantic Segmentation with Hyperspectral Images
    Fernando Peña, Pilar Vidal Aguilar, Darı́o Suárez Gracia, and 1 more author
    In ROBOT 2022: Fifth Iberian Robotics Conference - Advances in Robotics, Volume 1, Zaragoza, Spain, 23-25 November 2022, 2022
    DOI

2021

  1. A learning experience toward the understanding of abstraction-level interactions in parallel applications
    Alejandro Valero, Ruben Gran Tejero, Darı́o Suárez Gracia, and 6 more authors
    J. Parallel Distributed Comput., 2021
    DOI
  2. Analytical Model for Memory-Centric High Level Synthesis-Generated Applications
    Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, Marı́a Villarroya-Gaudó, and 1 more author
    IEEE Trans. Computers, 2021
    DOI
  3. On the use of many-core Marvell ThunderX2 processor for HPC workloads
    Vı́ctor Soria Pardos, Adrià Armejach, Darı́o Suárez Gracia, and 1 more author
    J. Supercomput., 2021
    DOI
  4. A Cross-Platform OpenVX Library for FPGA Accelerators
    Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, Marı́a Villarroya-Gaudó, and 3 more authors
    In 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021, Valladolid, Spain, March 10-12, 2021, 2021
    DOI
  5. RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU
    Yamilka Toca-Dı́az, Alejandro Valero, Ruben Gran Tejero, and 1 more author
    CoRR, 2021

2020

  1. DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files
    Alejandro Valero, Darı́o Suárez Gracia, and Ruben Gran Tejero
    IEEE Access, 2020
    DOI
  2. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform
    Andrés Rodrı́guez, Angeles G. Navarro, Rafael Asenjo, and 4 more authors
    J. Supercomput., 2020
    DOI
  3. An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis
    Maria Angelica Davila Guzman, Ruben Gran Tejero, Marı́a Villarroya-Gaudó, and 1 more author
    In 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020, Fayetteville, AR, USA, May 3-6, 2020, 2020
    DOI
  4. Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis
    Maria Angelica Davila Guzman, Ruben Gran Tejero, Marı́a Villarroya-Gaudó, and 1 more author
    CoRR, 2020

2019

  1. A fault-tolerant last level cache for CMPs operating at ultra-low voltage
    Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darı́o Suárez Gracia, and 3 more authors
    J. Parallel Distributed Comput., 2019
    DOI
  2. Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs
    Andrés Rodrı́guez, Angeles G. Navarro, Rafael Asenjo, and 4 more authors
    J. Syst. Archit., 2019
    DOI
  3. An Aging-Aware GPU Register File Design Based on Data Redundancy
    Alejandro Valero, Francisco Candel, Darı́o Suárez Gracia, and 2 more authors
    IEEE Trans. Computers, 2019
    DOI
  4. Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL
    Maria Angelica Davila Guzman, Raúl Nozal, Ruben Gran Tejero, and 3 more authors
    J. Supercomput., 2019
    DOI
  5. Simultaneous multiprocessing in a software-defined heterogeneous FPGA
    José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, and 5 more authors
    J. Supercomput., 2019
    DOI
  6. Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA
    José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, and 5 more authors
    J. Supercomput., 2019
    DOI
  7. Exposing Abstraction-Level Interactions with a Parallel Ray Tracer
    Alejandro Valero, Darı́o Suárez Gracia, Ruben Gran Tejero, and 14 more authors
    In Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA 2019, Phoenix, AZ, USA, June 22, 2019, 2019
    DOI

2018

  1. Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems
    Maria Angelica Davila Guzman, Ruben Gran Tejero, Marı́a Villarroya-Gaudó, and 1 more author
    In 2018 International Conference on High Performance Computing & Simulation, HPCS 2018, Orleans, France, July 16-20, 2018, 2018
    DOI
  2. Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems
    José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, and 5 more authors
    CoRR, 2018
  3. AISC: Approximate Instruction Set Computer
    Alexandra Ferreron, Jesús Alastruey-Benedé, Darı́o Suárez Gracia, and 1 more author
    CoRR, 2018

2017

  1. Abstract Representation of Shared Data for Heterogeneous Computing
    Tushar Kumar, Aravind Natarajan, Wenjia Ruan, and 3 more authors
    In Languages and Compilers for Parallel Computing - 30th International Workshop, LCPC 2017, College Station, TX, USA, October 11-13, 2017, Revised Selected Papers, 2017
    DOI
  2. Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip
    José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodrı́guez, and 4 more authors
    In Parallel Computing is Everywhere, Proceedings of the International Conference on Parallel Computing, ParCo 2017, 12-15 September 2017, Bologna, Italy, 2017
    DOI
  3. Exploiting Data Compression to Mitigate Aging in GPU Register Files
    Francisco Candel, Alejandro Valero, Salvador Petit, and 2 more authors
    In 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, Campinas, Brazil, October 17-20, 2017, 2017
    DOI

2016

  1. Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs
    Marta Ortı́n-Obón, Darı́o Suárez Gracia, Marı́a Villarroya-Gaudó, and 2 more authors
    J. Parallel Distributed Comput., 2016
    DOI
  2. Analysis of network-on-chip topologies for cost-efficient chip multiprocessors
    Marta Ortı́n-Obón, Darı́o Suárez Gracia, Marı́a Villarroya-Gaudó, and 2 more authors
    Microprocess. Microsystems, 2016
    DOI
  3. Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage
    Alexandra Ferrerón-Labari, Darı́o Suárez Gracia, Jesús Alastruey-Benedé, and 2 more authors
    IEEE Trans. Computers, 2016
    DOI

2015

  1. Concurrency in Mobile Browser Engines
    Calin Cascaval, Pablo Montesinos-Ortego, Behnam Robatmili, and 1 more author
    IEEE Pervasive Comput., 2015
    DOI

2014

  1. Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping
    Darı́o Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, and 2 more authors
    ACM Trans. Archit. Code Optim., 2014
    DOI
  2. Dynamic construction of circuits for reactive traffic in homogeneous CMPs
    Marta Ortı́n, Darı́o Suárez Gracia, Marı́a Villarroya-Gaudó, and 2 more authors
    In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014
    DOI
  3. Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages
    Alexandra Ferrerón-Labari, Darı́o Suárez Gracia, Jesús Alastruey-Benedé, and 2 more authors
    In 26th IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014, Paris, France, October 22-24, 2014, 2014
    DOI

2013

  1. Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors
    Alexandra Ferrerón-Labari, Marta Ortı́n-Obón, Darı́o Suárez Gracia, and 2 more authors
    In Architecture of Computing Systems - ARCS 2013 - 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings, 2013
    DOI
  2. Characterization and cost-efficient selection of NoC topologies for general purpose CMPs
    Marta Ortı́n, Alexandra Ferreron, Jorge Albericio, and 4 more authors
    In Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013, 2013
    DOI

2012

  1. LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors
    Darı́o Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, and 2 more authors
    IEEE Trans. Very Large Scale Integr. Syst., 2012
    DOI
  2. Automatic discovery of performance and energy pitfalls in HTML and CSS
    Adrian Sampson, Calin Cascaval, Luis Ceze, and 2 more authors
    In Proceedings of the 2012 IEEE International Symposium on Workload Characterization, IISWC 2012, La Jolla, CA, USA, November 4-6, 2012, 2012
    DOI

2009

  1. Light NUCA: A proposal for bridging the inter-cache latency gap
    Darı́o Suárez Gracia, Teresa Monreal, Fernando Vallejo, and 2 more authors
    In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009
    DOI
  2. SigRace: signature-based data race detection
    Abdullah Muzahid, Darı́o Suárez Gracia, Shanxiang Qi, and 1 more author
    In 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, 2009
    DOI

2007

  1. A proposal to introduce power and energy notions in computer architecture laboratories
    Alicia Ası́n Pérez, Darı́o Suárez Gracia, and Vı́ctor Viñals Yúfera
    In Proceedings of the 2007 Workshop on Computer Architecture Education, WCAE 2007, San Diego, California, USA, Saturday, June 9, 2007, 2007
    DOI