Summary / Resumen

Six of our papers published in conferences and journals have been cited by 27 patents and patent applications (23 patent families) from 7 companies and 2 institutions, which shows that these research results have had a real impact on industrial technology development. They comprise 22 granted patents and 5 applications, published between 2010 and 2026. In 17 of the 23 families the citation was included by the applicant, and in 2 the patent examiner rated our paper as particularly relevant (category X or Y).

Seis de nuestros artículos publicados en congresos y revistas han sido citados por 27 patentes y solicitudes de patente (23 familias) de 7 empresas y 2 instituciones, lo que muestra que estos resultados de investigación han tenido un impacto real en el desarrollo tecnológico de la industria. Son 22 patentes concedidas y 5 solicitudes, publicadas entre 2010 y 2026. En 17 de las 23 familias la cita la incluyó el propio solicitante, y en 2 el examinador de la patente consideró nuestro artículo especialmente relevante (categoría X o Y).

Companies/Empresas: IBM, ARM, Qualcomm, AMD, Synopsys, Ddaim, Google.
Institutions/Instituciones: Wuhan University of Technology, Institute of Software (Chinese Academy of Sciences).

Of the six cited papers, one was published in a journal and five in conferences. The journal paper, [4] (IEEE Transactions on Computers, 2016), has been cited by 3 patents (3 families); the conference papers, by 24 patents (20 families), most of them citing [3] (SBAC-PAD 2008; 14 patents in 12 families).

De los seis artículos citados, uno se publicó en revista y cinco en congresos. El de revista, [4] (IEEE Transactions on Computers, 2016), ha sido citado por 3 patentes (3 familias); los de congreso, por 24 patentes (20 familias), la mayoría de ellas a [3] (SBAC-PAD 2008; 14 patentes en 12 familias).

Cited papers / Artículos citados

The papers are listed below by year of publication. For each paper, patent families are listed from most recent to oldest, each headed by its most recent member.

A continuación se presentan los artículos por año de publicación. Para cada artículo, las familias de patentes van de la más reciente a la más antigua, encabezadas por su publicación más reciente.

[1] Speculative Early Register Release

J. Alastruey, T. Monreal, V. Viñals, M. Valero.
3rd ACM International Conference on Computing Frontiers (CF’06), ACM, 2006.
Ranking: GGS Class 3 (B-) (GII-GRIN-SCIE 2018).
DOI: 10.1145/1128022.1128061

Cited by 1 patent (1 family) / Citado por 1 patente (1 familia):

• Qualcomm — Use of Register Renaming System for Forwarding Intermediate Results Between Constituent Instructions of an Expanded Instruction.
  US 7669039 B2 (2010-02-23). Examiner / Examinador.

[2] Microarchitectural Support for Speculative Register Renaming

J. Alastruey, T. Monreal, V. Viñals, M. Valero.
IEEE International Parallel and Distributed Processing Symposium (IPDPS 2007), IEEE, 2007.
Ranking: CORE A (ERA 2008); GGS Class 2 (A) (GII-GRIN-SCIE 2018).
DOI: 10.1109/IPDPS.2007.370237

Cited by 5 patents (4 families) / Citado por 5 patentes (4 familias):

• IBM — Tracking Operand Liveness Information in a Computer System and Performing Function Based on the Liveness Information.
  US 10078515 B2 (2018-09-18); same family/misma familia: EP 2764433 A4 (2015-06-24). Applicant and examiner / Solicitante y examinador.
• ARM — Technique for Freeing Renamed Registers.
  US 9400655 B2 (2016-07-26). Applicant / Solicitante.
• ARM — Tracking Speculative Execution of Instructions for a Register Renaming Data Store.
  US 9361111 B2 (2016-06-07). Applicant / Solicitante.
• Qualcomm — Freeing Physical Registers in a Microprocessor.
  WO 2015/142435 A1 (2015-09-24). Examiner / Examinador.

[3] Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

J. Alastruey, T. Monreal, F. Cazorla, V. Viñals, M. Valero.
20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2008), IEEE, Campo Grande, Brazil, 2008.
Ranking: CORE B (ERA 2008).
DOI: 10.1109/SBAC-PAD.2008.17

Cited by 14 patents (12 families) / Citado por 14 patentes (12 familias):

• IBM — Coalescing Global Completion Table Entries in an Out-of-Order Processor.
  US 11204772 B2 (2021-12-21); same family/misma familia: US 10564979 B2 (2020-02-18). Applicant / Solicitante.
• IBM — Head and Tail Pointer Manipulation in a First-In-First-Out Issue Queue.
  US 10942747 B2 (2021-03-09). Applicant / Solicitante.
• IBM — Scalable Dependency Matrix with a Single Summary Bit in an Out-of-Order Processor.
  US 10929140 B2 (2021-02-23). Applicant / Solicitante.
• IBM — Block Based Allocation and Deallocation of Issue Queue Entries.
  US 10922087 B2 (2021-02-16). Applicant / Solicitante.
• IBM — Buffered Instruction Dispatching to an Issue Queue.
  US 10901744 B2 (2021-01-26). Applicant / Solicitante.
• IBM — Issue Queue with Dynamic Shifting Between Ports.
  US 10884753 B2 (2021-01-05). Applicant / Solicitante.
• IBM — Scalable Dependency Matrix with Wake-Up Columns for Long Latency Instructions in an Out-of-Order Processor.
  US 10802829 B2 (2020-10-13). Applicant / Solicitante.
• IBM — Completing Coalesced Global Completion Table Entries in an Out-of-Order Processor.
  US 10572264 B2 (2020-02-25). Applicant / Solicitante.
• IBM — Scalable Dependency Matrix with Multiple Summary Bits in an Out-of-Order Processor.
  US 10564976 B2 (2020-02-18). Applicant / Solicitante.
• IBM — Privilege Level Aware Processor Hardware Resource Management Facility.
  US 9342337 B2 (2016-05-17); same family/misma familia: US 8695010 B2 (2014-04-08). Applicant / Solicitante.
• IBM — Indicating Disabled Thread to Other Threads When Contending Instructions Complete Execution to Ensure Safe Shared Resource Condition.
  US 9047079 B2 (2015-06-02). Applicant / Solicitante.
• IBM — Processor with Hardware Thread Control Logic Indicating Disable Status When Instructions Accessing Shared Resources Are Completed for Safe Shared Resource Condition.
  US 8615644 B2 (2013-12-24). Applicant / Solicitante.

12 of them are listed at/12 de ellas figuran en IEEE Xplore → Citations → Patents. US 9342337 B2, a continuation of US 8695010 B2, is not included there/US 9342337 B2, continuación de US 8695010 B2, no figura en esa lista.

[4] Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

A. Ferrerón, D. Suárez-Gracia, J. Alastruey-Benedé, T. Monreal-Arnal, P. Ibáñez.
IEEE Transactions on Computers, vol. 65, no. 3, pp. 755–769, March 2016.
JCR 2016: Q1 (10/52, Computer Science, Hardware & Architecture).
DOI: 10.1109/TC.2015.2479585

Cited by 3 patents (3 families) / Citado por 3 patentes (3 familias):

• Synopsys — Memory Write Assist.
  US 12243585 B1 (2025-03-04). Applicant / Solicitante.
• AMD — Method and Apparatus for Using Compression to Improve Performance of Low Voltage Caches.
  US 10884940 B2 (2021-01-05). Examiner / Examinador.
• Wuhan University of Technology — Caching Multi-Bit Hard Error Detection and Fault Tolerance Device and Method Under Near Threshold Voltage.
  CN 108182125 A (2018-06-19). Examiner (X) / Examinador (X).

[5] Developing an AI IoT Application with Open Software on a RISC-V SoC

E. Torres-Sánchez, J. Alastruey-Benedé, E. Torres-Moreno.
35th Conference on Design of Circuits and Integrated Systems (DCIS 2020), IEEE, Segovia, Spain, pp. 1–6, 2020.
DOI: 10.1109/DCIS51330.2020.9268645

Cited by 3 patents (2 families) / Citado por 3 patentes (2 familias):

• Ddaim — Modular SoC AI/ML Inference Engine with Dynamic Updates Using a Central Collecting and Consolidated Layer-to-Layer Data Transfer Topology at Each Neural Network Layer.
  US 12602576 B2 (2026-04-14); same family/misma familia: US 12353987 B1 (2025-07-08). Applicant / Solicitante.
• Institute of Software (CAS) — YOLOv3 Target Detection Method Based on Domestic Intelligent Chip K210 and Electronic Device.
  CN 112580627 A (2021-03-30). Examiner / Examinador.

[6] Berti: an Accurate Local-Delta Data Prefetcher

A. Navarro-Torres, B. Panda, J. Alastruey-Benedé, P. Ibáñez, V. Viñals-Yúfera, A. Ros.
55th IEEE/ACM International Symposium on Microarchitecture (MICRO 2022), IEEE, Chicago, IL, USA, pp. 975–991, October 2022.
Ranking: GGS Class 2 (A) (GII-GRIN-SCIE 2021).
DOI: 10.1109/MICRO56248.2022.00072

Cited by 1 patent (1 family) / Citado por 1 patente (1 familia):

• Google — Dynamic Distance Adjustment for Stride Prefetcher.
  WO 2025/090058 A1 (2025-05-01). Examiner (Y) / Examinador (Y).

Notes / Notas

Patent families: simple families (EPO DOCDB) according to Lens.

Familias de patentes: familias simples (DOCDB de la EPO) según Lens.

Kind codes (letter after the number): B = granted patent; A = application.

Códigos de tipo (letra tras el número): B = patente concedida; A = solicitud.

Citation origin (end of each entry): Applicant = included by the applicant; Examiner = added in the search report or examination. Search report categories: X = particularly relevant if taken alone; Y = particularly relevant if combined with other documents.

Origen de la cita (al final de cada entrada): Solicitante = incluida por el propio solicitante; Examinador = añadida en el informe de búsqueda o en el examen. Categorías del informe de búsqueda: X = especialmente relevante por sí solo; Y = especialmente relevante combinado con otros documentos.

Data Sourced from The Lens: https://www.lens.org/ (retrieved on 2026-11-01).

Datos obtenidos de The Lens: https://www.lens.org/ (consultados el 2026-11-01).

Jefferson, O. A. et al. (2018). Mapping the global influence of published research on industry and innovation. Nature Biotechnology 36, 31–39. DOI: 10.1038/nbt.4049

Other sources/Otras fuentes: IEEE Xplore.