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FPGA accelerator for Gradient Boosting Decision Trees (GBDT)

Authors: Adrián Alcolea, Javier Resano
Creation date: 04 de Febrero de 2021
Repository: FPGA_accelerator_for_GBDT
Description: This repository contains the GBDT models and the source codes of the accelerator developed and described in the paper "FPGA Accelerator for Gradient Boosting Decision Trees", available on:


Authors: Juan Segarra Flor
Creation date: Nov 6, 2020
Repository: polygaz
Description: Code for obtaining safe data access patterns and reuse information for WCET analysis using Abstract Interpretation.

Tiling matrix transposition

Authors: Juan Segarra Flor
Creation date: Jan 16, 2020
Repository: Tiling matrix transposition
Description: Code for measuring the time required by a tiled in-place matrix transposition.

bvSFM (bit-vector sampled FM-index): a tool for sequence alignment

Authors: José Manuel Herruzo, Jesús Alastruey Benedé, Pablo Ibáñez Marín
Creation date: May 20, 2019
Repository: bvSFM: a tool for sequence alignment
Description: bvSFM (bit-vector sampled FM-index) is a tool for sequence alignment. Specifically, it implements an exact search algorithm that counts the number of matches of arbitrary length reads on a reference genome. bvSFM indexes a genome with an FM Index (based on the Burrows-Wheeler Transform or BWT). FM Index is a compact data structure suitable for fast matches of short reads to large reference genomes. For the human genome, its memory footprint is typically around 3.2 gigabytes of RAM. bvSFM uses an optimized FM-index data structure layout and codification that packs all relevant data needed in a query step within a single cache block, minimizing the memory bandwidth demand. bvSFM achieves best results when executed on multicore systems integrating high bandwidth memory, for instance an Intel Xeon Phi processor KNLa (codenamed Knights Landing, or KNL).

Pipelined architecture for sparse DNNs

Authors: Adrián Alcolea, Javier Olivito, Javier Resano
Creation date: February 04, 2019
Repository: Pipelined architecture for sparse DNNs
Description: VHDL code of an accelerator for Convolutionary Neural Networks that takes advantage of sparsity (large number of zeros) to work with compressed filters and avoid operations with a zero in at least one of the operands.


Authors: Gaddiel Desirena López, Lorena Rubio Anguiano, Antonio Ramírez Treviño, José Luis Briz
Creation date: October 22, 2018
Web page: Thermal-aware Energy-efficient Real TIme MUltiprocessor Scheduling Simulator
Description: Tertimuss (Thermal-aware Energy-efficient Real TIme MUltiprocessor Scheduling Simulator) is a simulation environment for designing and testing Real Time multiprocessor schedulers subject to thermal constraints. It consist of four modules. The fist module allows defining the system (processors, tasks) and their parameters. The second module automatically build a TCPN model, generating the state and thermal equations. The third module is for selecting, modifying or adding and parameterizing the scheduling algorithm. The fourth module allows the user to perform simulations and collect, process and plot results. The parameters of the tasks can be defined either manually or automatically (by means of the integrated UUnifast algorithm).

Última actualización el Jueves, 04 de Febrero de 2021 13:19