Projects- Piregrid (2009-2012)
PireGrid is a Spain-France border cooperation project funded by the European program Interreg IV A POCTEFA. The PireGrid participants are BIFI (Institute for Biocomputation and Physics of Complex Systems, Zaragoza) with the role of Lead Partner, the I3A (Aragón Institute of Engineering Research, Zaragoza), ITA (Technological Institute of Aragón, Zaragoza), LIUPPA (Laboratoire Informatique de l'Université de Pau et des Pays de l'Adour), IRIT (´Institut de Recherche en Informatique de Toulousse), and the Chambre de Commerce et d´Industrie Pau Béarn. This project involves the creation of a fully functional grid computing platform in the regions of Aragón, Navarra, Aquitaine and Midi-Pyrénées, making the most of the high knowledge of the technology partners. The project has demonstrated its operation and potential in the regional industry, especially for the small and medium enterprises, accomplishing several success cases in areas of Engineering, Data Mining and Aerospace. In the last year, the project focused also on cloud technologies, spreading them among the industrial partners.
- HiPEAC3 (January 2012 –December 2015)
European Network of Excellence on High Performance and Embedded Architecture and Compilation. Ref. FET ICT-287759. European FP7-ICT Framework Programme for Research and Technological Development in Computing Systems (ICT-2011.3.4). 3.81 M€. NoE coordinator: Koen De Bosschere - Univ. Ghent - Belgium
The HiPEAC's mission is to:
- Steer and increase the European research in the area of high-performance and embedded computing systems.
- Stimulate cooperation between academia and industry, and, computer architects and tool builders.
- Interconnection and Memory in Scalable Computers (2011 – 2013)
IP: Víctor Viñals-Yúfera (gaz-I3A). In collaboration with the Universidad de Cantabria, Santander, Spain. Funded by Spanish Ministry on Science and Innovation and ERDF (TIN2010-21291-C02-01).
Concerning memory hierarchy, we propose to research on second-level and last-level shared caches (shared LP-NUCAs, hardware prefetching and replacement algorithms), memory hierarchy in GPGPUs (performance modelling, power consumption and thermal properties). We also propose caches for real-time systems, accurately characterizing the WCET for a greater number of components and proposing non-conventional management policies oriented to static analyzability. In addition, we look for new cache organizations at several levels, considering interconnection networks on-chip, specialized in servicing and migrating cache blocks.
- Supercomputing and eScience, SyEC (2007-2013)
IP: Mateo Valero, UPC, BSC-CNS. Funded by Spanish Goverment (Consolider-Ingenio 2010, CSD2007-00050).
SyEC offers a national framework for putting together research groups expert in supercomputing applications with hardware/software machine designers. A list of projects goals follows:
- Advancing supercomputing through collaboration between users and designers of hardware and software for supercomputers.
- Encouraging the interrelationship between groups of researchers from the project.
- Encouraging the creation of a broad culture of supercomputing in Spain.
- Influencing the design and efficient use of supercomputers.
