My research interests are on systems, from hardware to software, but always close to the former. Within this broad area, computer architecture, memory hierarchy, and heterogeneous systems are the topics where I have worked the most.

publications

These are some of my publications in reversed chronological order. For the full list, please find me at Google Scholar and DBLP

2021

  1. A Cross-Platform OpenVX Library for FPGA Accelerators Dávila-Guzmán, Maria Angélica, Tejero, Ruben Gran, Villarroya-Gaudó, Marı́a, Gracia, Darı́o Suárez, Kalms, Lester, and Göhringer, Diana In 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021, Valladolid, Spain, March 10-12, 2021 2021

2020

  1. DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files Valero, A., Suárez-Gracia, D., and Gran-Tejero, R. IEEE Access 2020
  2. On the use of many-core Marvell ThunderX2 processor for HPC workloads Soria-Pardos, Víctor, Armejach, Adrià, Suárez Gracia, Darío, and Moretó, Miquel The Journal of Supercomputing 2020
  3. An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis Dávila-Guzmán, M. A., Tejero, R. G., Villarroya-Gaudó, M., and Suárez Gracia, D. In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2020

2019

  1. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform Rodríguez, Andrés, Navarro, Angeles, Asenjo, Rafael, Corbera, Francisco, Gran, Rubén, Suárez, Darío, and Nunez-Yanez, Jose The Journal of Supercomputing 2019
  2. Exploring Heterogeneous Scheduling for Edge Computing with CPU and FPGA MPSoCs Rodríguez, Andrés, Navarro, Angeles, Asenjo, Rafael, Corbera, Francisco, Gran, Rubén, Suárez, Darío, and Nunez-Yanez, Jose Journal of Systems Architecture 2019
  3. Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL Dávila Guzmán, María Angélica, Nozal, Raúl, Gran Tejero, Rubén, Villarroya-Gaudó, María, Suárez Gracia, Darío, and Bosque, Jose Luis The Journal of Supercomputing 2019
  4. A fault-tolerant last level cache for CMPs operating at ultra-low voltage Ferrerón, Alexandra, Alastruey-Benedé, Jesús, Suárez Gracia, Darío, Monreal Arnal, Teresa, Ibáñez Marín, Pablo, and Viñals Yúfera, Víctor Journal of Parallel and Distributed Computing 2019
  5. An Aging-Aware GPU Register File Design Based on Data Redundancy Valero, A., Candel, F., Suárez-Gracia, D., Petit, S., and Sahuquillo, J. IEEE Transactions on Computers 2019

2018

  1. Simultaneous multiprocessing in a software-defined heterogeneous FPGA Nunez-Yanez, Jose, Amiri, Sam, Hosseinabady, Mohammad, Rodríguez, Andrés, Asenjo, Rafael, Navarro, Angeles, Suarez, Dario, and Gran, Ruben The Journal of Supercomputing 2018
  2. Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems: Invited Paper Dávila Guzmán, M. A., Grán Tejero, R., Villarroya Gaudo, M., and Suárez Gracia, D. In International Workshop on Exploitation of high performance Heterogeneous Architectures and Accelerators (WEHA) as part of 2018 International Conference on High Performance Computing Simulation 2018
  3. Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems Nunez-Yanez, J., Hosseinabady, M., Amiri, M., Rodrı́guez, A., Asenjo, R., Navarro, A., Gran-Tejero, R., and Suárez-Gracia, D. ArXiv e-prints 2018
  4. AISC: Approximate Instruction Set Computer Ferrerón-Labari, Alexandra, Alastruey-Benedé, Jesús, Gracia, Darı́o Suárez, and Karpuzcu, Ulya In The 2018 Workshop on Approximate Computing Across the Stack (WAX) co-located with ASPLOS 2018

2017

  1. Exploiting Data Compression to Mitigate Aging in GPU Register Files Candel, F., Valero, A., Petit, S., Suárez-Gracia, D., and Sahuquillo, J. In In 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) 2017

2016

  1. Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs Ortı́n-Obón, Marta, Suárez Gracia, Darı́o, Villarroya-Gaudó, Marı́a, Izu, Cruz, and Viñals, Vı́ctor J. Parallel Distrib. Comput. 2016
  2. Analysis of network-on-chip topologies for cost-efficient chip multiprocessors Ortı́n-Obón, Marta, Gracia, Darı́o Suárez, Villarroya-Gaudó, Marı́a, Izu, Cruz, and Yúfera, Vı́ctor Viñals Microprocessors and Microsystems - Embedded Hardware Design 2016
  3. Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage Ferrerón-Labari, Alexandra, Gracia, Darı́o Suárez, Alastruey-Benedé, Jesús, Arnal, Teresa Monreal, and Ibáñez, Pablo IEEE Trans. Computers 2016

2015

  1. Concurrency in Mobile Browser Engines Cascaval, Calin, Montesinos-Ortego, Pablo, Robatmili, Behnam, and Gracia, Darı́o Suárez IEEE Pervasive Computing 2015

2014

  1. Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping Gracia, Darı́o Suárez, Ferrerón-Labari, Alexandra, Campo, Luis Montesano Del, Arnal, Teresa Monreal, and Yúfera, Vı́ctor Viñals TACO 2014
  2. Dynamic construction of circuits for reactive traffic in homogeneous CMPs Ortı́n, Marta, Gracia, Darı́o Suárez, Villarroya-Gaudó, Marı́a, Izu, Cruz, and Viñals, Vı́ctor In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014 2014
  3. Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages Ferrerón-Labari, Alexandra, Gracia, Darı́o Suárez, Alastruey-Benedé, Jesús, Arnal, Teresa Monreal, and Viñals, Vı́ctor In 26th IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014, Paris, France, October 22-24, 2014 2014

2013

  1. Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors Ferrerón-Labari, Alexandra, Ortı́n-Obón, Marta, Gracia, Darı́o Suárez, Alastruey-Benedé, Jesús, and Yúfera, Vı́ctor Viñals In Architecture of Computing Systems - ARCS 2013 - 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings 2013

2012

  1. LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors Gracia, Darı́o Suárez, Dimitrakopoulos, Giorgos, Arnal, Teresa Monreal, Katevenis, Manolis, and Yúfera, Vı́ctor Viñals IEEE Trans. VLSI Syst. 2012
  2. Automatic discovery of performance and energy pitfalls in HTML and CSS Sampson, Adrian, Cascaval, Calin, Ceze, Luis, Montesinos, Pablo, and Gracia, Darı́o Suárez In Proceedings of the 2012 IEEE International Symposium on Workload Characterization, IISWC 2012, La Jolla, CA, USA, November 4-6, 2012 2012

2009

  1. Light NUCA: A proposal for bridging the inter-cache latency gap Gracia, Darı́o Suárez, Monreal, Teresa, Vallejo, Fernando, Beivide, Ramón, and Viñals, Vı́ctor In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009 2009
  2. SigRace: signature-based data race detection Muzahid, Abdullah, Gracia, Darı́o Suárez, Qi, Shanxiang, and Torrellas, Josep In 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA 2009

2007

  1. A proposal to introduce power and energy notions in computer architecture laboratories Pérez, Alicia Ası́n, Gracia, Darı́o Suárez, and Yúfera, Vı́ctor Viñals In Proceedings of the 2007 Workshop on Computer Architecture Education, WCAE 2007, San Diego, California, USA, Saturday, June 9, 2007 2007

intellectual property

While working at industry, we filled some patents. For a detailed list please visit WIPO or google patents.