I am interested in the development of efficient hardware support for Neural Networks. In particular, Convolutional Neural Networks used for the classification of Hyperspectral images.
Due to sparsity, a significant percentage of the operations carried out in Convolutional Neural Networks (CNNs) contains a zero in at least one of their operands. We propose the implementation in an FPGA of an architecture for CNNs capable of taking advantage of sparsity in two different ways: compressing sparse matrices and avoiding multiplications with zero in their operands.
The aim of this research is to develop efficient solutions capable of processing hyperspectral images on-board at real-time. For its achievement, we will explore the use of CNNs and their optimization trough the development of specific hardware support, based on FPGAs.