| E. Torres, P. Ibáñez, V. Viñals and J.M. Llabería |
| "Store Buffer Design for Multibanked Data Caches" |
| IEEE Transactions on Computers October 2009, vol. 58 no. 10, pp.1307-1320. ISSN: 0018-9340. link |
| B. Sahelices, P. Ibáñez, V. Viñals and J.M. Llabería |
| "A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors" |
| Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. LNCS 5704, pp. 149-161. |
| ISBN 978-3-642-03868-6. AR=33%. pdf |
| D. Suarez, T. Monreal, F. Vallejo, R. Beivide and V. Viñals |
| "Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap" |
| Proceedings of the 12th Design, Automation & Test in Europe Conference (DATE'09), Acropolis, Nice, France, April 20-24, 2009. AR=23% |
| ISBN: 978-3-9810801-5-5, ISSN: 1530-1591.pdf |
| A. Muzahid, D. Suárez, Shanxiang Qi y J. Torrellas |
| "SigRace: signature-based data race detection" |
| Proceedings of the 36th annual international symposium on Computer architecture (ISCA'09), pp. 337-348. Austin, TX, USA, June 20-24, 2009. |
| ISBN 978-1-60558-526-0, AR=20% pdf |
| Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez and Víctor Viñals |
| "Multi-level Adaptive Prefetching based on Performance Gradient Tracking" |
| The 1st JILP Data Prefetching Championship (DPC-1), Raleigh, North Carolina - February 14-18, 2009 pdf (Best Paper Award) |
| Jesús Alastruey, Teresa Monreal, Francisco Cazorla, Víctor Viñals y Mateo Valero |
| "Selection of the Register File Size and the Resource Allocation Policy on SMT Processors" |
| Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, Oct 29-Nov 1, 2008. |
| IEEE Computer Society, pp. 63-70, ISBN 978-0-7695-3423-7, AR=39% pdf |
| V. Cholvi and J. Segarra |
| "Analysis and Placement of Storage Capacity in Large Distributed Video Servers". |
| Computer Communications, Volume 31, Issue 15, 25 September 2008, Pages 3604-3612. link |
| Ramos, L.M, Briz, J.L., Ibáñez, P. and Viñals, V. |
| "Low-cost Adaptive Data Prefetching" |
| LNCS - Procs. of 14th International European Conference on Parallel and Distributed Computing (Euro-Par 2009). August 26-29, 2008, Las Palmas de Gran Canaria, Spain. DOI= http://dx.doi.org/10.1007/978-3-540-85451-7_36 AR=34% pdf slides |
| L. C. Aparicio, J. Segarra, C. Rodríguez, J. L. Villarroel, and V. Viñals |
| "Avoiding the WCET Overestimation on LRU Instruction Cache" |
| Proceedings of the IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 25-27 August 2008, Kaohsiung, Taiwan, p.p 393-398. IEEE Computer Society. ISBN 978-0-7695-3349-0. AR=36%. pdf |
| B.Sahelices, P. Ibáñez, V. Viñals and J.M. Llabería. |
| "Critical Sections Characterization in Splash-2 Applications for DSM Multiprocessors". |
| ACACES 2008, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 13-19, pp. 49-52. Academia Press, ISBN 978 90 382 1288 3 pdf |
| Ramos, L. M., Briz, J. L., Ibáñez, P. E., and Viñals, V. 2007. Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News 35, 4 (Sep. 2007), 37-44. DOI= http://doi.acm.org/10.1145/1327312.1327319 |
| Ana Bosque, Pablo Ibañez, Víctor Viñals, Per Stenström, Jose M. Llabería |
| "Characterization of Apache web server with Specweb2005" |
| Proceedings of the 8th MEDEA Workshop held in conjunction with the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT) , Brasov, Romania, September 15-19, 2007. pp. 73-80. ACM ISBN: 978-1-59593-807-7 |
| A. Asín, D. Suárez, and V. Viñals |
| "A Proposal to Introduce Power and Energy Notions in Computer Architecture Laboratories" |
| Proceedings of the Workshop on Computer Architecture Education 2007 held in conjunction with the 34th International Symposium on Computer Architecture (ISCA), San Diego, California, USA, June 9th, 2007. |
| J. Alastruey, T. Monreal, V. Viñals and M. Valero |
| "Microarchitectural Support for Speculative Register Renaming" |
| Proceedings of the 21st IEEE International Parallel & Distributed Processing Symposium (IPDPS 2007), Long Beach, California USA, 26-30 March 2007. |
| Abstracts: IEEE Computer Society, p. 45, ISBN 1-4244-0909-8. Full paper: CD-ROM, IEEE Computer Society, 10 p., ISBN 1-4244-0910-1. AR=26%. pdf |
| J. Segarra and V. Cholvi |
| "Convergence of periodic broadcasting and video-on-demand". |
| Computer Communications, Volume 30, Issue 5 , 8 March 2007, Pages 1136-1141. link |
| Ramos, L.M, Briz, J.L., Ibáñez, P. and Viñals, V. |
| "Data prefetching in a cache hierarchy with high bandwith and capacity". |
| Procs. of the MEDEA Workshop. Seattle, USA, Sept. 2006. pdf |
| J. Alastruey, J.L. Briz, P. Ibáñez and V. Viñals |
| "Software Demand, Hardware Supply". |
| IEEE Micro Jul./Aug. 2006, Vol. 26, No. 4. link (pdf) slides |
| B. Sahelices, A. de Dios, P. Ibáñez, V. Viñals y J.M. Llabería |
| "Speeding-up Synchronizations in DSM Multiprocessors" |
| Proceedings of the 12th International Euro-Par Conference. August/September 2006. |
| A. Bosque, V. Viñals, P. Ibáñez, P. Stenstrom and J.M. Llabería |
| "Cache Miss Characterization of Commercial Workloads" |
| ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 23-29, pp. 201-204. Academia Press, ISBN 90 382 0981 9. |
| L. C. Aparicio, J. Segarra, J. L. Villarroel y V. Viñals |
| "WCET Computation in Presence of Caches" |
| ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 23-29, pp. 205-208. Academia Press, ISBN 90 382 0981 9. |
| J. Alastruey, T. Monreal, V. Viñals and M. Valero |
| "Speculative Early Register Release" |
| Proceedings of the 3rd conference on Computing frontiers (CF), Ischia, 3-5 May 2006, pp 291-302, ISBN:1-59593-302-6, ACM Press. AR=25%. link |
| M. J. Garzarán, M. Prvulovic, J. M. Llabería, V. Viñals, L. Rauchwerger and J. Torrellas |
| "Tradeoffs in Buffering Multi-Version Memory State for Speculative Thread-Level Parallelization in Multiprocessors" |
| ACM Transactions on Architecture and Code Optimization (TACO), vol. 2, issue 3 (September 2005), pp 247-279, ISSN:1544-3566 2005 |
| A. Bosque, V. Viñals, J.M. Llabería y Per Stenström |
| "Accurate and Complexity-Effective Coherence Predictors" |
| ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 25-29, pp. 91-94. Academic Press, ISBN 90 382 0802 2. |
| D. Suárez, T. Monreal y V. Viñals |
| "Improvements on Wire Delay Tolerant Caches" |
| ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 25-29, pp. 111-114. Academic Press, ISBN 90 382 0802 2. |
| J. Alastruey, T. Monreal, V. Viñals and M. Valero |
| "Efficient Register File Management in High-ILP Processors" |
| ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 25-29, pp. 201-204. Academic Press, ISBN 90 382 0802 2. |
| E. Torres, P. Ibáñez, V. Viñals and J.M. Llabería |
| "Store Buffer Design in First-Level Multibanked Data Caches" |
| 32nd Annual International Symposium on Computer Architecture (ISCA 2005), Madison, Wisconsin USA, June 4-8, 2005, pp. 469-480. AR=23%. |
| IEEE Computer Society Press (ISBN 0-7695-2270-X/05) |
| T. Monreal, V. Viñals, J. González, A. González and M. Valero |
| "Late Allocation and Early Release of Physical Registers" |
| IEEE Transactions on Computers, vol. 53, no. 10, pp. 1244-1259, October 2004. pdf |
| T. Monreal, V. Viñals, A. González and M. Valero |
| Hardware Support for Early Register Release |
| Int. Journal of High Performance Computing and Networking (IJHPCN), Special Issue on Improving Performance in Parallel Systems, vol. 3, issue 2/3, pp. 83-94, ISSN (print/online): 1740-0562 / 1740-0570. |
| Editor: Inderscience Publishers (Geneve, Switzerland), Sept.-Oct. 2004 preface link |
| E. Torres, P. Ibáñez, V. Viñals and J.M. Llabería |
| "Contents Management in First-Level Multibanked Data Caches" |
| 10th International Euro-Par Conference, LNCS 3149, pp 516-524. August/September 2004. |
| J. Segarra and V. Cholvi |
| "On-line Advancements of Transmission Plans in Video-on-Demand" |
| 24th International Conference on Distributed Computing Systems Workshops, pp 158-163. March 2004. ps |
| M.J. Garzarán, M. Prvulovic, J.M. Llabería, V. Viñals, L. Rauchwerger and J. Torrellas |
| "Software Logging under Speculative Parallelization", pp. 181-193. |
| Chapter 12 of Part III (Software-Based memory Tuning) in book: High-Performance Memory Systems. ISBN: 0-387-00310-X High Performance Memory Systems. |
| Editors: H. Hadimiouglu, D. Kaeli , J. Kuskin , A. Nanda and J. Torrellas. Nov. 2003, Springer-Verlag (New York). |
| M.J. Garzarán, M. Prvulovic, V. Viñals, J.M. Llabería, L. Rauchwerger, J. Torrellas |
| "Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation" |
| 12th. International Conference on Parallel Architectures and Compilation Techniques (PACT-2003) pp. 170-181 Septiembre 2003. pdf |
| E. Torres, P. Ibáñez,V. Viñals and J.M. Llabería |
| "Counteracting Bank Missprediction in Sliced First-Level Caches" |
| 9th International Euro-Par Conference, LNCS 2790, pp 586-596. August 2003 pdf |
| M.J. Garzarán, M.Prvulovic, J.M. Llabería, V. Viñals, L. Rauchwerger and J. Torrellas |
| "Tradeoffs in Buffering Multi-Version Memory State for Speculative Thread-Level Parallelization in Multiprocessors" |
| Proc. of the Int. Symp. on High-Performance Computer Architecture, pages 191-202, Febrero 2003. AR=22%. pdf |
| T. Monreal, V. Viñals, A.González and M. Valero |
| "Hardware Schemes for Early Register Release" |
| Proc. of the International Conference on Parallel Processing. Vancouver, Canada. August 18-21, 2002, pp. 5-13. AR=36%. ps |
| F. Dang, M.J. Garzarán, M. Prvulovic, Y. Zhang, A. Jula, H. Yu, N. Amato, L. Rauchwerger and J. Torrellas |
| "SmartApps, an Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations " |
| Workshop on Next Generation Systems (junto con el IPDPS 2002). Sponsored by the NSF Next Generation Software Program, Fort Lauderdale (Florida, USA), April 15, 2002. ps |
| M.J. Garzaran, M. Prvulovic, A. Jula, H. Yu, Y. Zhang, L. Rauchwerger and J. Torrellas |
| "Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors" |
| International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2001. AR=21%. ps |
| M.J. Garzarán, M. Prvulovic, J. M. Llaberia, V. Viñals, L.Rauchwerger and J. Torrellas |
| "Software Logging under Speculative Parallelization" |
| Workshop on Memory Performance Issues, June 2001. ps (versión extendida de este artículo en LNCS: pdf) |
| M. Prulovic, M.J. Garzaran, L. Rauchwerger, and J. Torrellas |
| "Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization" |
| Proc. of the 28th Annual Int. Symp. on Computer Architecture (ISCA), 2001. AR=15%. ps |
| M.J. Garzarán, J. Briz, P. Ibáñez and V. Viñals |
| "Hardware Prefetching in Bus-based Multiprocessors: Pattern Characterization and Cost-Effective Hardware" |
| In Proc. of the IX Euromicro Workshop on Parallel and Distributed Processing, Euro-PDP 2001, paginas 345- 354, Feb. 2001. AR=42%. ps |
| T. Monreal, A. González, M. Valero, J. González and V. Viñals |
| "Dynamic Register Renaming Through Virtual-Physical Registers" |
| The Journal of Instruction-Level Parallelism, vol. 2, May 2000. ps |
| L. Ramos, P. Ibáñez, V. Viñals and J.M. Llabería |
| "Modelling Load Address Behaviour Through Recurrences" |
| In Proc. of ISPASS 2000, IEEE Int. Symp. on Performance Analysis of Systems and Software, April 24-25, 2000, Austin, Texas. pp. 101-108. AR:29%. pdf |
| T. Monreal, A. González, M. Valero, J. González and V. Viñals |
| "Delaying Physical Register Allocation Through Virtual-Physical Registers" |
| In Proc. of the MICRO-32, Annual Int. Symp. on Microarchitecture. Haifa, Israel. Nov. 16-18, 1999, pp. 186-192. AR=21%. ps |
| P. Ibáñez, V. Viñals, J.L. Briz, and M.J. Garzarán |
| "Characterization and Improvement of Load/Store Cache-based Prefetching" |
| In Proc. of Int. Conf. on Supercomputing, ICS'98, July 13-17, 1998, Melbourne, Australia. pp.369-376. AR=47% ps |
| A. González, M. Valero, J. González and T. Monreal |
| "Virtual Registers" |
| In Proc. of Int. Conf. on High-Performance Computing, pp. 364-369, 1997. Mean AR(2000-02)=35%. ps |
| P. Ibáñez and V. Viñals |
| "Performance Assesment of Contents Mangement in Multilevel on-chip Caches" |
| In Proc. of the 22nd. Euromicro Int. Conf., pp. 431-440, Praga (Czech Rep.), Sept. 1996. ps |
| L.M. Jimeno-Ochoa, P. Ibáñez and V. Viñals |
| "Warm Time Sampling: Fast and Accurate Simulation of Cache Memory" |
| In Proc. of the 22nd. Euromicro Int. Conf. Short Contributions, pp. 39-44, Praga (Czech Rep.), Sept. 1996. ps |
| S. Gutierrez, O. Benedí, Darío Suárez, Jose María Marín, and Víctor Viñals |
| "Forge: A Multi-purpose Platform for Measuring Energy and Temperature in Commodity PCs" |
| XX Jornadas de Paralelismo, La Coruña (España), 16-18 Sept. 2009. |
| Actas pp. 403-408, ISBN: 84-9749-346-8. pdf |
| Editores: R. Doallo, M. Arenaz y P. González (Universidade da Coruña) |
| J. Ortiz, D. Suárez, V. Viñals, María Villarroya-Gaudó |
| "Nanotubos de Carbono para conexiones en Caches: Arquitecturas más allá del CMOS" |
| XX Jornadas de Paralelismo, La Coruña (España), 16-18 Sept. 2009. |
| Actas pp. 271-276, ISBN: 84-9749-346-8. pdf |
| Editores: R. Doallo, M. Arenaz y P. González (Universidade da Coruña) |
| J. Alastruey, T. Monreal, M. Valero y V. Viñals |
| "Implementación de un Predictor de Último Uso con Decaimiento" |
| XX Jornadas de Paralelismo, La Coruña (España), 16-18 Sept. 2009. |
| Actas pp. 171-176, ISBN: 84-9749-346-8. pdf |
| Editores: R. Doallo, M. Arenaz y P. González (Universidade da Coruña) |
| L. C. Aparicio, J. Segarra, C.Rodríguez, J. L. Villarroel y V. Viñals |
| "Tightening the WCET Bound through Path Pruning" |
| XIX Jornadas de Paralelismo, Castellón (España), 17-19 Sep. 2008. |
| Actas pp. 565-570, ISBN 978-84-8021-676-0. pdf |
| Editores: J. M. Badía, F. D. Igual, E. S. Quintana y G. Quintana (Universitat Jaume I) |
| Jesús Alastruey, Teresa Monreal, Francisco Cazorla, Víctor Viñals y Mateo Valero |
| "Selección del Tamaño del Banco de Registros y de la Política de Asignación de Recursos en Procesadores SMT" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 3-10, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| Darío Suárez Gracia, Teresa Monreal Arnal y Víctor Viñals Yúfera |
| "Improving performance by merging cache levels" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 83-90, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| Juan Antonio Victorio, Enrique F. Torres Moreno y Victor Viñals Yúfera |
| "Vatios: Simulador de Procesador con Estimación de Potencia" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 115-122, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| Esther Rodríguez, Benjamín Sahelices, Diego R. Llanos, Pablo Ibáñez, Víctor Viñals y José M. Llabería |
| "Aceleración del cambio de propietario de un cerrojo en multiprocesadores DSM" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 139-146, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| Ana Bosque, Pablo Ibáñez, Víctor Viñals, Per Stenström y José M. Llabería |
| "Memory Characterization of Apache using Specweb2005" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 165-172, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| Luis C. Aparicio, Juan Segarra, José L. Villarroel, Víctor Viñals y Clemente Rodríguez |
| "Instruction Fetch Contribution to Exact WCET in Systems with Cache" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 809-816, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| Alicia Asín, Darío Suárez y Víctor Viñals |
| "Introducing Energy and Power in Computer Architecture Laboratories" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 885-892, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| Francisco Sanmartín, Enrique Torres, Juan Segarra y Unai Arronategui |
| "El uso de encaminadores domésticos en el entorno docente" |
| XVIII Jornadas de Paralelismo (II Congreso Español de Informática, CEDI 2007), Zaragoza (España). 12-14 Sept. 2007. |
| Actas pp. 939-946, ISBN vol 1: 978-84-9732-672-8. ISBN obra completa: 978-84-9732-593-6. pdf |
| Editores: P. Ibáñez, E. Torres, J. Segarra, J. Alastruey y L.M. Ramos |
| L. C. Aparicio, J. Segarra, J. L. Villarroel y V. Viñals |
| "Execution Path Pruning for WCET Analysis" |
| XVII Jornadas de Paralelismo, Albacete (España). Sep. 2006. pdf |
| Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez y Víctor Viñals |
| "Prebúsqueda de datos basada en DFCM" |
| XVII Jornadas de Paralelismo, Albacete (España). Sep. 2006. pdf |
| L. C.. Aparicio, J. Segarra, J. L. Villarroel y V. Viñals |
| "Cálculo del WCET en Presencia de Memorias Cache" |
| IX Jornadas de Tiempo Real, Valladolid (España). pp. 4, 9-10 Feb. 2006. pdf |
| L. C.. Aparicio, J. Segarra, J. L. Villarroel y V. Viñals |
| "Cálculo del Peor Caso en la Cache de Datos" |
| XVI Jornadas de Paralelismo (CEDI 2005), Granada (España). pp. 329.336, 13-16 Sep. 2005. pdf |
| L. C.. Aparicio, J. Segarra, J. L. Villarroel y V. Viñals |
| "Memorias Cache en Sistemas de Tiempo Real" |
| XIII Jornadas de Tiempo Real, Bilbao (España). pp. 251-258, 3-4 Feb. 2005. pdf |
| J. Alastruey, T. Monreal, M. Valero y V. Viñals |
| "Limits on Early Release of Physical Registers" |
| XV Jornadas de Paralelismo, Almería (España). pp. 231-236, 15-17 Sept. 2004. pdf |
| J. Alastruey, O. Blasco, P.Ibáñez, J.L. Briz y V. Viñals |
| "SPEC CPU y Caches en Chip: Evolución e Interacción" |
| XIII Jornadas de Paralelismo, Lérida (España). pp. 19-24, 9-11 Sept. 2002. pdf |
| J. Alastruey, O. Blasco, A. Hurtado, P. Ibáñez, y V. Viñals |
| "COVI: Computador Virtual" |
| XIII Jornadas de Paralelismo, Lérida (España). 9-11 Sept. 2002. (presentación, no está en actas) pdf |
| F. Latorre, E.F. Torres, P. Ibáñez y V. Viñals |
| "Generación Precisa de Caminos Especulativos sobre Shade (SPARC v9)" |
| XII Jornadas de Paralelismo, Valencia (España). pp. 21-26, 3-4 Sept. 2001. ps |
| T. Monreal, A. González, V. Viñals y M. Valero |
| "Liberacion anticipada de registros" |
| XI Jornadas de Paralelismo", 11-13 Sept. 2000, Granada (España). ps |
| E.F. Torres, J.L. Briz, O. Pastor y V. Viñals |
| "Aplicaciones Multimedia en Pentium-II: Impacto en el rendimiento de su Cache de Datos" |
| En actas de X Jornadas de Paralelismo, Murcia (España). pp. 51-54, 13-15 Sept. 1999. pdf |
| E.F. Torres y V. Viñals |
| "Extensiones Multimedia al Lenguaje Máquina en Procesadores de Propósito General" |
| En actas de IX Jornadas de Paralelismo, San Sebastian (España). pp. 251-258, 2-4 Sept. 1998. pdf |
| M.J. Garzarán, V. Viñals, J.L. Briz y A. Orío |
| "Caracterización del tráfico en protocolos de coherencia snoopy" |
| En actas de las VIII Jornadas de Paralelismo, pag. 111-120, Cáceres (España), 10-12 Sept. 1997. ps |
| L.M. Ramos |
| "Alternativas de Diseño en Sistemas de Prebúsqueda Hardware de Datos" |
| Tesis Doctoral. Dpto. Informática e Ingeniería de Sistemas, U. de Zaragoza. Diciembre 2009. pdf |
| J. Alastruey |
| "Renombre de Registros Especulativo" |
| Tesis Doctoral. Dpto. Informática e Ingeniería de Sistemas, U. de Zaragoza. Diciembre 2009. pdf |
| E. Torres |
| "Alternativas de Diseño en Memoria Cache de Primer Nivel Multibanco" |
| Tesis Doctoral. Dpto. Informática e Ingeniería de Sistemas, U. de Zaragoza. Junio 2005. pdf |
| T. Monreal |
| "Técnicas Hardware para Optimizar el Uso de los Registros en Procesadores Superescalares" |
| Tesis Doctoral. Dpto. Informática e Ingeniería de Sistemas, U. de Zaragoza. Junio 2003. pdf |
| M.J. Garzarán |
| "Hardware Prefetch, Reduction Support, and Speculative State Buffering in Shared Memory Multiprocessors" |
| Tesis Doctoral. Dpto. Informática e Ingeniería de Sistemas, U. de Zaragoza. Junio 2002. pdf |
| P. Ibáñez |
| "Gestión Multinivel y Prebúsqueda Hardware en Memorias Cache Integradas" |
| Tesis Doctoral. Dpto. Informática e Ingeniería de Sistemas, U. de Zaragoza. Julio 1998. ps |
| Ramos, L.M, Briz, J.L., Ibáñez, P. and Viñals, V. |
| "Low-Cost Adaptive Data Prefetching" |
| Report interno DIIS (Universidad de Zaragoza), RR-08-03, Abril 2008, 10 páginas. |
| B. Sahelices, E. Rodríguez, P. Ibáñez, V. Viñals, and J.M. Llabería |
| "Caracterización de Secciones Críticas SPLASH-2 en Multiprocesadores DSM" |
| Report interno DIIS (Universidad de Zaragoza), RR-07-15, Noviembre 2007, 23 páginas. pdf |
| E. Torres, P. Ibañez, V. Viñals, and and J.M. Llabería |
| "Tolerating the Update Delay in a Bank Predictor" |
| Report interno DIIS (Universidad de Zaragoza), RR-07-01, 2007, 22 páginas. Difusión restringida. |
| Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Victor Viñals |
| "Data prefetching in a cache hierarchy with high bandwidth and capacity" |
| Report interno DIIS (Universidad de Zaragoza), RR-06-09, Julio 2006, 8 páginas. |
| B. Sahelices, A. de Dios, P. Ibáñez, V. Viñals y J.M. Llabería |
| "Speeding-up Synchronizations in DSM Multiprocessors" |
| Report interno DIIS (Universidad de Zaragoza), RR-06-07, Mayo 2006, 12 páginas. pdf |
| E. Torres, P. Ibáñez, V. Viñals y J.M. Llabería |
| "Store Buffer Design in First-Level Multibanked Data Caches" |
| Report interno DIIS (Universidad de Zaragoza), RR-04-04, Octubre 2004, ¿? páginas |
| B. Sahelices, A. de Dios, P. Ibáñez, V. Viñals y J.M. Llabería |
| "Reducción de la Latencia de Lectura Mediante Predicción de Última Escritura en Multiprocesadores" |
| Report interno DIIS (Universidad de Zaragoza), RR-04-07, Septiembre 2004, 4 páginas pdf |
| E. Torres, P. Ibáñez, V. Viñals y J.M. Llabería |
| "Distributed Forwarding Store Buffer in First-Level Multibanked Data Caches" |
| Report interno DIIS (Universidad de Zaragoza), RR-04-03, Julio 2004, ¿? páginas |
| J. Alastruey, J.L. Briz, P.Ibáñez y V. Viñals |
| "The Memory Side of Moore's Law" |
| Report interno DIIS (Universidad de Zaragoza), RR-03-09, Dic 2003, 15 páginas |
| D. Suárez Gracia, L. Pozzi, P. Ienne, V. Viñals |
| "Developing a back-end for the ARM v5 architecture within the machine SUIF infrastructure" |
| Report interno DIIS (Universidad de Zaragoza), RR-03-08, Dic 2003, 20 páginas pdf source code |
| B. Sahelices, A. de Dios, P. Ibáñez, V. Viñals y J.M. Llabería |
| "Autoinvalidación Mejorada Utilizando Predicción de Último Toque" |
| Report interno DIIS (Universidad de Zaragoza), RR-03-10, Junio 2003, 6 páginas pdf |
| M.J. Garzarán, M. Prvulovic, J.M. Llabería, V. Viñals, L. Rauchwerger, and J. Torrellas |
| "Software Logging for Multi-Version Buffering under Speculative Parallelization" |
| Report interno DIIS (Universidad de Zaragoza), RR-02-04, Abril 2002, 13 páginas |
| T. Monreal, V. Viñals, A. González and M. Valero |
| "Early Register Release" |
| Report interno DIIS (Universidad de Zaragoza), RR-01-01, pág. 1-21. 2001. ps |
| M. Karlsson, P. Ibáñez and L.M. Ramos |
| "Limitations of Hardware Data Prefetching Techniques on Emerging Application Domain" |
| Technical Report no.99-12, Department of Computer Engineering, Chalmers University of Technology, 1999. Pendiente de publicación. http://www.ce.chalmers.se/~karlsson/papers/hard_prefetch.ps ps |
| T.Monreal, A.Gonzalez, M.Valero, J.Gonzalez and V.Vinyals |
| "Delaying Physical Register Allocation Through Virtual-Physical Registers" |
| Report de Investigación. UPC-DAC-1999-20 / UPC-CEPBA-1999-12. págs. 1-18, 1999 ps reports DAC |
| T. Monreal, A.González, M. Valero y V. Viñals |
| "Registros Virtuales" |
| Report interno DIIS, RR-99-08, 1999. ps |
| A.Gonzalez, M.Valero, J.Gonzalez, and T.Monreal |
| "Virtual Registers" |
| Report de Investigación. UPC-DAC-1997-55 / UPC-CEPBA-1997-20. págs. 1-6, 1997. reports DAC |
| P. Ibáñez y V. Viñals |
| "SPAR prefetch and prefetch combining, two proposals for hardware data prefetching" |
| Report interno DIIS, RR-97-01, 1997. ps |
| L.M. Jimeno, P. Ibáñez y V. Viñals |
| "Comparación de estrategias de simulación de jerarquías de memoria" |
| Report interno GISI, RR-95-08, 1995. ps |